Pulse or digital communications – Multilevel – Synchronized
Patent
1995-09-19
1997-12-09
Tse, Young T.
Pulse or digital communications
Multilevel
Synchronized
375290, 375375, 360 51, H04L 2549
Patent
active
056967934
ABSTRACT:
Disclosed is a phase difference detection circuit for detecting a phase difference between an equalized signal obtained by equalizing an extended partial-response class-4 signal and a sampling clock. This phase difference detection circuit has a sample hold circuit for sampling and holding the equalized signal at the sampling clock, a comparator circuit for comparing the sampled and held signals with at least four slice levels and converting them into determination level signals having at least quinary values and a phase difference generation circuit for generating a phase difference on the basis of at least the quinary determination level signals from the comparator circuit and outputs of the sample hold circuit. The EPR-4 signals are quinary-determined, and it is therefore possible to measure the phase difference by accurately detecting a peak position or a zero cross position of the signal.
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patent: 4890299 (1989-12-01), Dolivo et al.
patent: 5216554 (1993-06-01), Schneider
patent: 5265125 (1993-11-01), Ohta
patent: 5267267 (1993-11-01), Kazawa et al.
Fujitsu Limited
Tse Young T.
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