Phase detector with linear gain selection

Details Phase detector with linear gain selection Phase detector with linear gain selection

2000-09-12

2002-09-10

Sherry, Michael (Department: 2829)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

Frequency of cyclic current or voltage

C324S076790, C324S621000, C377S020000, C702S074000

Reexamination Certificate

active

06448755

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to frequency synthesizers, phase locked loops, phase detectors, and more specifically to a phase detector with a linear gain selection capability.
Phase locked loops and circuits for implementing such loops are well known in the art for providing frequency selective outputs that are easily controlled, adjustable, and stable in operation. In particular, a phase locked loop (PLL) generally includes a voltage controlled oscillator (VCO) having an output frequency that is dependent upon the voltage applied to a control input to the VCO. The output of the voltage controlled oscillator provides a selected frequency as a desired output and also provides feedback to one input of a phase detector. The phase detector has a second input that receives a reference frequency. The phase detector compares the VCO output to the reference frequency input and provides an output signal used to control the VCO through a loop filter such that the output frequency of the VCO is locked to the reference frequency. In this manner, the phase locked loop can be constructed to provide an output frequency that tracks the reference frequency input signal with a high degree of accuracy.
The phase-locked loop is a negative feedback system that is stabilized by controlling both the phase shift and gain within the loop. The phase shift is controlled by careful selection of the loop filter response parameters. The open loop bandwidth of the phase locked loop is controlled by gain compensation circuits. The open loop bandwidth and the phase margin of the phase locked loop determine phase noise spectrum, vibration susceptibility, and settling time of the PLL. The open loop bandwidth may be modified to improve these performance characteristics by the use of gain compensation circuits.
Several solutions exist in the art to provide gain compensation for phase locked loops. Commercially available devices such as the Analog Devices AD42XX series, for example, incorporate a programmable register to control a charge pump current source in a phase detector to control the gain.
U.S. Pat. No. 4,595,886 discloses a circuit for adjusting the AC loop gain and DC prepositioning in a phase locked loop. The system includes an in-phase and out-of-phase signal applied through exclusive-OR gate circuitry that includes inputs from a PROM to digitally adjust the AC gain in the phase locked loop. The PROM also stores digital values representing a desired DC prepositioning level. The PROM outputs with the digital values are coupled to the phase locked loop and converted to provide a signal summed with the AC signal to adjust the prepositioning level.
The prior art solutions yield hardware that controls the current or voltage at the phase detector output in a linear fashion. Since gain is a logarithmic function of these variables, linear current or voltage control yields a gain control characteristic that is non-linear.
What is needed is a phase locked loop with a gain adjustment capability to maintain a desired open loop gain bandwidth by providing a phase detector with a linear gain selection characteristic.
SUMMARY OF THE INVENTION
In accordance with the present invention, a phase detector having a linear gain characteristic output signal is disclosed. The phase detector comprises a first exclusive-OR gate with a first input connected to an input signal and a second input connected to a reference signal and a second exclusive-OR gate with a first input connected to an inverted input signal and a second input connected to the reference signal. A first plurality of switches has inputs connected to an output of the first exclusive-OR gate. A first plurality of resistors has a first terminal of each resistor connected to outputs of the first plurality of switches. A second plurality of switches has inputs connected to an output of the second exclusive-OR gate. A second plurality of resistors has a first terminal of each resistor connected to the outputs of the second plurality of switches. The first plurality of switches and the second plurality of switches have control inputs connected to gain selection signals to enable the switches in corresponding pairs. The resistors' second terminals are connected together and the resistors are selected in corresponding pairs by the corresponding pairs of switches to form a linear gain characteristic output signal in accordance with the gain selection signals. The phase detector may include a third exclusive-OR gate with a first input connected to the reference signal and a second input connected to a sense select signal. The third exclusive-OR gate output is connected to a second input of the first exclusive-OR gate and a second input of the second exclusive-OR gate to select the sense of the phase detector. Resistor values Ra of the first plurality of resistors are determined by the equation Ra=Rs/&agr;
i
and resistor values Rb of the second plurality of resistors corresponding to resistor values Ra are determined by the equation Rb=Rs/(1−&agr;
i
).
It is an object of the present invention to provide a gain adjustment capability to a phase locked loop that is linear.
It is an advantage of the present invention to provide a phase detector with linear gain selection capability.
It is a feature of the present invention to easily provide linear gain selection with complementary resistor pairs.


REFERENCES:
patent: 3678252 (1972-07-01), Payne
patent: 4118674 (1978-10-01), Ball
patent: 4404530 (1983-09-01), Stryer
patent: 4595886 (1986-06-01), Mroch

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