Phase detector with edge-sensitive enable and disable

Details Phase detector with edge-sensitive enable and disable Phase detector with edge-sensitive enable and disable

1995-05-03

1996-12-10

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

327 12, 327 7, H03D 1300

Patent

active

055834582

ABSTRACT:
An integrated circuit utilizing a symmetric phase detection circuit for detecting a phase relationship between a reference clock signal and a delayed clock signal. The integrated circuit described herein features a control block circuit coupled to receive the reference clock signal and an enable check signal. The control block circuit generates an enable signal which provides the present invention with the ability to detect the phase difference between signals having the same frequency or signals that differ in frequency by a rational factor. The control block circuit generates the enable signal in response to the enable check signal and the reference clock signal. The enable signal, the reference clock signal, and the delayed clock signal are coupled to the phase detection circuit. In response to the enable signal, the phase detection circuit then determines the phase relationship between the reference clock signal and delayed clock signal.

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patent: 5317202 (1994-05-01), Waizman
patent: 5386437 (1995-01-01), Yasuda
patent: 5408200 (1995-04-01), Buhler

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