Pulse or digital communications – Testing – Phase error or phase jitter
Reexamination Certificate
1998-12-28
2002-11-19
Chin, Stephen (Department: 2634)
Pulse or digital communications
Testing
Phase error or phase jitter
C375S375000, C375S376000, C327S012000
Reexamination Certificate
active
06483871
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for electrical signal phase detection and a system incorporating the same.
BACKGROUND TO THE INVENTION
Digital communication equipment is used in a wide variety of devices for the transmission of digital information. Such information includes numerical data in computers and digital encodings of voice in telecommunications systems.
In the course of transmission of digital signals from a transmitter to a receiver, the digital signals tend to become degraded. Degradation may involve loss of overall strength of the signal, and loss of definition of the pulse edges: at the time of sending, the pulse edges typically rise and fall sharply with respect to the overall pulse length giving a cleanly defined shape to the pulse whilst, at the receiver, the rate of rise and fall of the pulses tends to decrease resulting in less sharply defined pulses. In order to correct for these degradations, it is common practice to regenerate the original digital signal from the distorted one at the receiving end of a digital communication link. The regenerated signal may then be retransmitted along a further transmission link or be further processed locally.
To regenerate a received signal, typically, the receiver must ensure that the received data signal (the data signal) is processed synchronously relative to a local clock signal (the clock signal). It is also desirable to ensure that the data signal is not sampled near the degraded edges of the received data pulses which would lead to incorrect interpretation of the signal. Typically a phase locked loop would be used, containing a phase detector, an adjustable oscillator, and feedback circuit so that the receiver tends to a target clock-to-data phase relationship (the set point) which is not easily adjustable.
Alternatively in some circumstances a delay locked loop could be used, comprising a phase detector, a clock signal source, an adjustable delay in the clock or data path, and feedback circuit so that the receiver tends to a target clock-to-data phase relationship (the set point) which typically is not easily adjustable.
The target relationship may not be optimum, for example where the eye of the received data signal is asymmetrical.
It is known to make a compensating adjustment by means of one or more delays introduced into one or more paths leading from the clock signal or data signal to the phase detector or decision circuit. This has the disadvantage that it requires the delay circuitry to operate at the full speed of the clock or data signal, with associated hardware costs, power consumption, and crosstalk which can act to degrade the data or clock signal before it reaches the decision circuit and/or phase detector.
It is also known to add an offset in the phase locked or delay locked loop, for example by adding a voltage to the phase detector output, thereby directly affecting the loop feedback input signal. This has the disadvantages of being susceptible to pattern-dependent jitter, and operating only over a limited phase range.
A clock-to-data phase detector is a device which takes as two of its inputs a data signal and a clock signal and generates signals giving information about the phase difference between the data signal and clock signal. A known means of representing the phase difference information is by means of a pair of signals: the first signal (the phase difference signal) comprises a component which represents the phase difference and a further component which represents the variations in the number of edges occurring in the data; the second signal (the reference signal) represents only the latter variation. Subsequent subtraction of the reference signal from the phase signal gives a signal (the difference signal) representing the difference in phase.
It is known [from C. R. Hogge, “A Self Correcting Clock Recovery Circuit”, Journal of Lightwave Technology, Vol. LT-3, No. 6, December 1985] to generate a phase difference signal employing circuitry constructed using silicon components, whilst at the same time generating a reference signal by employing a fixed delay introduced by means of a delay line.
U.S. patent application Ser. Nos. 08/847,426 and 09/156,019 (Continuation-in-part) provide an improved method and apparatus for detecting the phase difference between a digital data signal and a clock signal. By ensuring that no pulse in the output phase signal is narrow enough to introduce a non-linearity, a source of non-linearity exhibited in previous known phase detectors is avoided. In addition, by ensuring that critical timing paths through the circuit contain similar circuit blocks, with similar propagation delays, relative time relationships are preserved from clock and data inputs to XOR inputs. The circuit is therefore largely insensitive to changes in the characteristics of the components so long as they all move together, as they would in an integrated circuit implementation.
U.S. Pat. No. 5,250,913 provides a phase detector for a phase locked loop for bit clock retrieval where the phase detector employs a plurality of variable unit delays and has a constant gain region that is a percentage of the clock period over an extended frequency range of the VCO enabling a single chip to operate for several applications at widely different frequencies.
OBJECT TO THE INVENTION
The invention seeks to provide an improved method and apparatus for detecting the phase difference between a digital data signal and a clock signal.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided a digital signal phase detector comprising: a data signal input for receiving a data signal; a clock signal input for receiving a clock signal; a set point control signal input for receiving a set point control signal indicative of a desired set point of the detector; a first circuit coupled to said data signal input and said clock signal input and arranged to provide a phase difference signal representative of both the clock period of the clock and the difference in phase between the clock and the data signal; a second circuit coupled to said data signal input and the clock signal input and arranged to provide a reference signal representative of the clock period of the clock signal; wherein at least one of said first and second circuits is coupled to said set point control signal and the corresponding output signal is representative of said set point control signal; and wherein a comparison of the phase difference signal with the reference signal provides an indication of the difference between the desired set point of the circuit and the phase difference between the clock and the data signal.
Advantageously, where the eye of the received signal is asymmetrical, the sampling point can be offset to the optimal sampling position.
Advantageously, whilst certain undesired delays may exist within a phase detector circuit or in circuitry leading to it, these can be compensated for.
Advantageously, the delay elements are arranged to act on regenerated digital signal pulses. The height and speed of such pulses are more predictable than those of the unregenerated data signal, and consequently the delay circuits work better.
Advantageously, the circuitry in the data and clock paths leading to the phase detector is minimised, thereby reducing power consumption, crosstalk, and improving overall performance.
Advantageously, the phase difference and reference signal pulses can be made to overlap whereby to reduce the data content to be filtered out of the error signal, thereby improving performance.
Preferably, the phase detector is arranged such that timing of pulse edges in said output signal of said at least one of said first and second circuits varies responsive to said set point control signal.
Preferably, said one of said first and second circuits comprises a first adjustable delay circuit coupled to said set point control signal, and arranged to introduce a signal delay responsive to said set point control signal, whereby to render
Chin Stephen
Lee Mann Smith McWilliams Sweeney & Ohlson
Lugo David B.
Nortel Networks Limited
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