Phase detector, phase comparator, and clock synchronizing...

Details Phase detector, phase comparator, and clock synchronizing... Phase detector, phase comparator, and clock synchronizing...

2011-07-05

2011-07-05

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S218000

Reexamination Certificate

active

07973581

ABSTRACT:
A flip-flop circuit includes: a first latch circuit that receives input of a data signal and a rise delay clock signal, raises a signal of a first node according to the fall of the rise delay clock signal, and lowers the signal of the first node according to the rise of the rise delay clock signal; a second latch circuit that receives input of the signal of the first node and the clock signal and lowers a signal of a second node at timing when the clock signal falls; a third latch circuit that receives input of the signal of the second node and the clock signal and generates an output signal for maintaining the data signal; and a pull-down circuit that pulls down the signal of the first node with the rise delay clock signal.

REFERENCES:
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Japanese Office Action issued Mar. 30, 2010 for corresponding Japanese Application No. 2008-047157.
Yuan, Jiren et al. “High-Speed CMOS Circuit Technique” IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989.
Larsson, Patrik et al. “Impact of Clock Slope on True Single Phase Clocked (TSPC) CMOS Circuits,” IEEE Journal of Solid-State Circuits, vol. 29, No. 6, Jun. 1994.

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