Phase detector for clock synchronization and recovery

Details Phase detector for clock synchronization and recovery Phase detector for clock synchronization and recovery

1996-04-17

1998-08-25

Chin, Wellington

Pulse or digital communications

Synchronizers

Self-synchronizing signal

375374, 327144, 327157, 327159, 331 17, H04L 702

Patent

active

057990484

ABSTRACT:
A clock recovery circuit employing a phase-locked loop design includes an N-to-1 multiplexer (MUX) coupled to a series of N latches which allows data to sampled at a frequency N times that of the clock. Incoming data is latched by each of the N latches, where each latch is clocked at a different phase of the clock signal such that the phase of the clock provided to the nth latch is shifted nT/N, where T is the period of the clock and n is an integer from 1 to N. The output terminals of the series of N latches are coupled to associated ones of input terminals of the N-to-1 MUX. The selection of MUX input terminals is controlled by the clock signal such that the incoming data signal is reconstructed at the output terminal of the MUX. In this manner, the incoming data signal is effectively sampled at N times the clock speed.

REFERENCES:
patent: 4222009 (1980-09-01), Moulton et al.
patent: 4227251 (1980-10-01), Kazama et al.
patent: 4305045 (1981-12-01), Metz et al.
patent: 4371974 (1983-02-01), Dugan
patent: 4380815 (1983-04-01), Clendening
patent: 4400667 (1983-08-01), Belkin
patent: 4400817 (1983-08-01), Summer
patent: 4535459 (1985-08-01), Hogge, Jr.
Hogge, Jr., "A Self Correcting Clock Recovery Circuit", Journal of Lightwave Technology vol. LT-3, No. 6, Dec. 1985.
Lee, "A 155-MHz Clock Recovery Delay- and Phase-Locked Loop", IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992.

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