Pulse or digital communications – Multilevel – Synchronized
Reexamination Certificate
2001-02-05
2004-12-07
Le, Amanda T. (Department: 2634)
Pulse or digital communications
Multilevel
Synchronized
C375S360000, C375S376000, C327S155000, C327S233000, C331S025000
Reexamination Certificate
active
06829309
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The invention is related to signal processing of a received multi-state signal such as a pulse amplitude modulated signal, and in particular to phase detection as part of the clock recovery of such a signal using a very low sampling rate such as the baud rate of the signal.
2. Background Art
In a serial data communication channel, the clock is embedded in the data or information (rather than being transmitted as a separate signal in parallel with the data). Therefore, a receiver must recover the transmitter's clock from the data-containing signal in order to process the data. Typically, this means that the receiver must be able to discern each edge in a pulse amplitude modulated signal (for example), compare it to the edge of a locally generated clock, and use this comparison, or “phase detection”, to adjust the local clock, until the local clock is frequency locked to the transmitter's clock and the phase of the local clock is optimally positioned so as to minimize the errors in recovering the data. When a DSP receiver is used, the most straight-forward way to ensure that this can happen is for the receiver to sample the received signal at a sampling rate much higher than the frequency of the transmitter's clock. In this way, the receiver can closely observe the zero-crossing time of each edge in the received signal, accurately perform phase detection with that zero-crossing and the phase of the local clock using conventional techniques, adjust the local clock, and thereby recover the exact frequency and phase of the transmitter's clock. Of course, such a high sampling rate (e.g., 5 or 10 times the baud rate of the received signal) is a luxury that a competitive system cannot easily afford. This is because, at least in part, the power consumption of the receiver increases with the sampling rate. Therefore, it would be desirable to reduce the sampling rate, but such a reduction would seem to entail a loss of accuracy in the determination of the zero-crossing of each edge. Such a loss of accuracy leads to clock recovery failure and therefore general failure-of the receiver.
Assuming such difficulties can be overcome, it would be desirable to sample a pulse amplitude modulated signal at a rate the same as or not significantly exceeding the symbol (baud) rate of the received signal. This may be thought of as sampling once per edge. It would be further desirable to be able to do this with a multi-state signal (e.g., a pulse amplitude modulated signal) which is allowed to change from any one of its allowed levels to any other allowed level within one clock period.
SUMMARY OF THE INVENTION
The invention is related to analog to digital conversion of a multi-level analog signal at a very low sampling rate. The analog signal is sampled by a local clock (the “recovered” clock) to produce a succession of samples of the analog signal. These samples themselves are used to adjust the phase and frequency of the local clock in a feedback loop known as “clock recovery.” Part of any clock recovery feedback loop is a phase detector that detects the difference in phase between the local clock and the clock that transmitted the signal that is being sampled. The low sampling rate may be within an order of magnitude of the symbol rate of the analog signal. Each sample is converted to a digital word. A phase detector reference circuit determines from peak values of the analog signal at least two allowable levels of the analog signal including a reference-crossing level. The phase detector defines a zero band of amplitude ranges of the analog signal including the reference-crossing level. It further defines an error band of amplitude ranges of the analog signal extending from said zero band to a fraction of the amplitude of the next allowable level. The phase detector then infers either a positive or negative phase error for each pair of successive samples of the analog signal. If the current and prior samples fall within the error and zero bands respectively, a negative phase error is inferred. If the current and prior samples fall within the zero and error bands respectively, a positive phase error is inferred. For any other values of the current and prior samples, the phase error is unknown.
A negative or positive phase error causes a phase correction feedback control loop to adjust the recovered clock. If the recovered clock is being generated by means of selecting a phase of a local clock, known to be very close in frequency to the far end transmitter clock, then the phase correction feedback control loop is used to increment or decrement the phase of the local clock. If the recovered clock is being generated by means of adjusting a local VCO, then the phase correction feedback control loop is used to adjust the voltage on the VCO.
Typically, there are three allowable levels determined by the determining step symmetrically disposed about zero amplitude. In-one embodiment, the phase detector takes the absolute value of each of the samples, whereby the pair of successive samples are absolute values of the digitized analog signal. The reference crossing level is zero amplitude and is a zero-crossing level.
The invention relies upon the randomness of the received signal in that no determination or correction of phase error is made if neither or both of the pair of samples are in the error band, since this condition will obtain sporadically and not continuously.
REFERENCES:
patent: 5121411 (1992-06-01), Fluharty
patent: 5872819 (1999-02-01), Carsello et al.
patent: 6127897 (2000-10-01), Sasaki
U.S. Appl. No. 09/636,047, Zortea et al., filed Aug. 10, 2000.
U.S. Appl. No. 09/636,042, Zortea et al., filed Aug. 10, 2000.
3Com Corporation
Le Amanda T.
Michaelson Peter L.
Michaelson & Associates
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