Phase detector for a delay locked loop and delay locked loop...

Details Phase detector for a delay locked loop and delay locked loop... Phase detector for a delay locked loop and delay locked loop...

2003-05-23

2004-10-26

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331S00100A, C327S012000, C327S156000, C327S158000, C327S159000

Reexamination Certificate

active

06809601

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a phase detector for a delay locked loop, in which a delay unit delays a periodic clock signal by an adjustable delay. The circuit has a first input for the periodic clock signal, a second input for the delayed clock signal, an UP output and a DOWN output. The phase detector outputs a first pulse signal at the UP output and a second pulse signal at the DOWN output—the signals respectively assuming a first or a second level—for the setting of the delay unit. The first pulse signal changes to the first level in the event of a positive edge of the clock signal and the second pulse signal changes to the first level in the event of a positive edge of the delayed clock signal. When both pulse signals are at the first level, a reset device sets both pulse signals to the second level.
Delay locked loops, also referred to as DLLs, serve to uniformly subdivide a period of a clock signal. This makes it possible to multiply a clock signal with regard to frequency. DLLs constitute an alternative to known phase locked loops (PLLS) for conditioning and frequency synthesis in the case of clock signals.
A DLL usually has a phase detector and a delay chain having, for example, 16 delay stages by way of which the clock signal can be divided into identical time units. In this case, the phase detector determines the phase between the input clock and the delayed clock signal output by the delay chain, determines from this an actuating signal for setting the delay of the delay chain or the delay stages thereof and applies the signal to the delay chain or the delay stages.
One example of such a phase detector is found, for example, in an article by A. Sharpe, “A 3-state phase detector can improve your next PLL design”, EDN Magazine, Sep. 20, 1976, pp. 224-28.
In the case of a DLL with a phase detector, a difficulty that may arise is that the delay of the delay chain makes up a multiple of a desired delay which usually amounts to a period of the clock signal. Since the output signal of the delay chain appears the same to the phase detector in this case as in the case of the desired delay, it can happen that the DLL effects regulation to an incorrect delay, namely to a multiple of the desired delay. This should be avoided, however.
This problem area becomes particularly significant against the background of broadband-action DLLs—sought in the meantime—which can process clock signals over a very large frequency range. In order to avoid incorrect locking-on in that context, DLLs with phase mixer circuits have been developed (cf. T. Lee et al., “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM”, IEEE Journal of Solid-State Circuits, Vol. 29, December 1994), but they require very complicated production processes. Moreover, digital approaches have been investigated but overall they exhibit unacceptable phase noise. This has been able to be improved in so-called mixed-mode DLLs (cf. S. Tanoi et al., “A 250-622 MHz Deskew and Jitter-Suppressed Clock Buffer Using Two-Loop Architecture”, IEEE Journal of Solid State Circuits, Vol. 31, April 1996), but they are unsatisfactory with regard to complexity and size and also power demand of the circuit.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a phase detector for a delay locked loop, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which avoids or reduces erroneous locking-on.
With the foregoing and other objects in view there is provided, in accordance with the invention, a phase detector for a delay locked loop having a delay unit for delaying a periodic clock signal by a settable delay, comprising:
a first input for the periodic clock signal, a second input for a delayed clock signal, an UP output for outputting a first pulse signal, a DOWN output for outputting a second pulse signal, and a reset device, the first and second signals respectively assuming a first level or a second level, for setting the delay unit, the first pulse signal changing to the first level with a positive edge of the clock signal and the second pulse signal changing to the first level with a positive edge of the delayed clock signal and, if the first and second pulse signals are at the first level, said reset device resets the first and second pulse signals to the second level;
a blocking device connected to tap off a partly delayed clock signal at the delay unit, the partly delayed clock signal being delayed relative to the clock signal less than the delayed clock signal, said blocking device being configured to prevent a resetting of the first pulse signal for at least half a period of the clock signal if a positive edge of the partly delayed clock signal occurs while the first pulse signal is at the first level.
In other words, the objects of the invention are achieved by way of a phase detector for a delay locked loop, in which a delay unit delays a periodic clock signal by a settable delay, having a first input for the periodic clock signal, a second input for the delayed clock signal, an UP output and a DOWN output, the phase detector outputting a first pulse signal at the UP output and a second pulse signal at the DOWN output, which signals can respectively assume a first or a second level, for the setting of the delay unit, the first pulse signal changing to the first level in the event of a positive edge of the clock signal and the second pulse signal changing to the first level in the event of a positive edge of the delayed clock signal and, in the event of both pulse signals being at the first level, a reset device setting both pulse signals to the second level, which phase detector has a blocking device, which taps off at the delay unit a partly delayed clock signal, which is delayed less than the delayed clock signal, and prevents a resetting of the first pulse signal for at least half a period of the clock signal if a positive edge of the partly delayed clock signal occurs while the first pulse signal is at the first level.
The invention is based on the insight that, in the event of erroneous locking-on, i.e. if the phase detector does not effect regulation to the desired delay of one period, but rather to a certain multiple thereof, the partly delayed pulse signal exhibits a positive edge during the duration of the first pulse signal, i.e. the UP pulse signal, or the duration of the second pulse signal, i.e. the DOWN pulse signal. Therefore, the phase detector according to the invention suitably evaluates a partly delayed clock signal and then alters the first pulse signal, i.e. the UP pulse signal. In this case, the phase detector outputs a lengthened first pulse signal and thus adjusts the delay locked loop in the direction of a shorter delay. It thus effects regulation to a shorter delay. Erroneous locking-on to a multiple of the desired delay thus becomes less likely or is avoided.
The blocking device of the phase detector prevents the delay locked loop from locking on to a multiple of the desired delay, i.e. to a multiple of the period of the clock signal, in that a positive edge of the partly delayed clock signal is detected and used for a suitable action. In this case, a positive edge is to be understood as a level change of the clock signal which corresponds to the level change at which the first or the second pulse signal is set to the first level. The positive edge will usually be a rising edge of a binary clock signal; of course, a falling edge is also possible.
In customary digital logic, a high or low level will be used respectively as the first or second level. The two levels thus correspond to the logic levels of digital technology. The lengthening of the first pulse signal results in the desired shifting of the delayed clock signal in the direction of a shorter delay. This effect may also be reinforced if the blocking device sets the second pulse signal to the second level as soon as a positive edge of the partly delayed clock signal occurs while the second p

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