Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
2005-03-14
2008-09-23
Fan, Chieh M. (Department: 2611)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C375S373000, C375S376000, C327S112000, C327S158000, C331S016000, C331S017000
Reexamination Certificate
active
07428284
ABSTRACT:
A delay-lock loop includes a dual mode phase detector. The dual mode phase detector includes a single edge phase detector that generates output signals indicative of the phase relationship between the rising edge of a reference signal and the rising edge of a feedback signal generated by the delay-lock loop. The dual mode phase detector also includes a dual edge phase detector that generates output signals indicative of the phase relationship between both the rising edge of a reference signal and the rising edge of the feedback signal and the falling edge of a reference signal and the falling edge of the feedback signal. A lock detector controls a switch so that it couples the output signals from the single edge phase detector to a delay line when the loop is locked, and it otherwise couples the output signals from the dual edge phase detector to the delay line.
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Dorsey & Whitney LLP
Fan Chieh M.
Pathak Sudhanshu C.
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