Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Patent
1993-11-01
1996-04-09
Chin, Stephen
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
375376, 324 2, H03D 100
Patent
active
055068740
ABSTRACT:
A phase detector 10 is disclosed herein. A clock signal CLK (OR I), a marker signal MARK (or Q) and a data signal D are provided. The data signal may comprise a periodic clock signal. Sampler circuitry 50 receives the clock signal CLK, the marker signal MARK and the data signal D and generates a sampled clock signal and a sampled marker signal. Sign modifier circuitry 52 then receives the sampled clock signal and sampled marker signal and generates first and second command signals. Select circuitry 54 receiving these command signals selects a valid command signal based upon the data signal.
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Lee et al., "A 155-MHz Clock Recovery Delay- and Phase-Locked Loop", IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992, pp. 1736-1746.
Izzard Martin J.
Scott David B.
Chin Stephen
Donaldson Richard L.
Ghebretinsae T.
Kesterson James C.
Matsil Ira S.
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