Phase detector

Details Phase detector Phase detector

1999-06-14

2001-07-10

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

C327S148000, C327S007000, C327S157000

Reexamination Certificate

active

06259278

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a phase detector, and more particularly, to a phase detector which can be utilized in a multi-phase-locked loop for data recovery.
BACKGROUND OF THE INVENTION
Due to the advancement in the network transmission technology and the demands in the installed base of the computer networks, the network data transmission rate in hardware environment has been increased. Therefore, it becomes more and more important to correctly recover data (clock signal).
Nowadays, a phase-locked loop is often utilized to recover data. During the data recovery process, usually the received data can be correctly recovered (read) by using a phase detector to synchronize the recovering clock and the received data at the receiving end. In other words, the phase detector plays a very important role in whether the data can be correctly recovered by a phase-locked loop.
As mentioned above,
FIG. 1
illustrates a prior art phase-locked loop
1
for data recovery comprising a phase detector
11
, a charge pump
12
, a loop filter
13
, and a voltage controlled oscillator
14
. The phase detector
11
is used to receive a data (clock) signal from outside and a feedback clock signal CK
vco
from the voltage controlled oscillator
14
. The phase detector
11
compares the two received signals, outputs a control signal up or dn according to the phase difference &thgr;
e
of the two received signals (&thgr;
e
=&thgr;
data
−&thgr;
clock
). The control signal up or dn is used to control the charge pump
12
. As shown in FIG.
2
(
a
), when the transition edge of the data (clock) signal data leads the falling edge of the feedback clock signal CK
vco
, the phase detector
11
outputs an up signal. On the other hand, as shown in FIG.
2
(
b
), when the transition edge of the data (clock) signal data lags behind the falling edge of the feedback clock signal CK
vco
, the phase detector
11
outputs a dn signal. The up and dn control signals outputted from the phase detector
11
control the charge/discharge operation of the charge pump
12
. A voltage signal Vd is generated by the charge pump
12
according to the up and dn control signals. The loop filter
13
generates a voltage Vc for controlling the voltage-controlled oscillator
14
. In accordance with the above-mentioned voltage Vc, the voltage-controlled oscillator
14
outputs a clock signal CK
vco
which is applied to the phase detector
11
.
Referring to
FIG. 3
, the phase detector
11
of the phase-locked loop
1
is constituted by four flip-flops
111
,
112
,
113
,
114
, and two OR gates
115
,
116
. The flip-flops
111
and
112
receive the inverted data signal {overscore (data)} from outside as well as the data itself, respectively. The clock signal CK
vco
from the voltage-controlled oscillator
14
is applied to the complementary reset terminals rb of the flip-flops
111
and
112
so as to output control signals up
1
and up
2
, respectively. The flip-flops
113
and
114
are utilized to receive the complementary data signal {overscore (data)} from outside and the data itself. The inverted signal of CK
vco
is applied to the complementary reset terminals rb of the flip-flops
113
and
114
so as to output control signals dn
1
and dn
2
, respectively. According to the control signals up
1
and up
2
, the OR gate
115
generates a control signal up (refer to FIG.
2
(
a
)) for controlling the charge pump
12
. Similarly, according to the control signals dn
1
and dn
2
, the OR gate
116
generates a control signal dn (as shown in FIG.
2
(
b
)) to control the charge pump
12
.
Referring to
FIG. 1
, the voltage Vd is controlled by the two received signals (up, dn) of the charge pump
12
. In other words, the variation of the control voltage Vd is related with the phase error &thgr;
e
.
FIG. 4
illustrates the relation between the variation of the voltage Vd and the phase error &thgr;
e
. As shown in
FIG. 4
, when the data signal data has a phase lagging behind the clock signal CK
vco
, the smaller the phase error &thgr;
e
is, the more the voltage Vd varies, which is contrary to our prediction. Theoretically, the phase error &thgr;
e
is supposed to approximate to zero and closely moves around the origin when a phase-locked loop nearly enter a phase-locked state. However, according to the above description, when the data signal data of a phase-locked loop has a phase lagging behind the clock signal CK
vco
, a rapid variation of the voltage Vd will be generated, which induces clock jitter. Tolerance for data random jitter thus become worse. In other words, it is impossible to reduce the clock jitter utilizing the conventional phase detector
11
, tolerance for data random jitter is thus hardly improved.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a phase detector without dead zone. Clock jitter thus can be reduced and tolerance for data random jitter can be improved.
Another object of the present invention is to provide a phase detector without static phase error.
The present invention provides a phase detector which outputs a plurality of control signals (up
i
's and dn
i
's) by utilizing a plurality of multi-phase clock signals to detect the transition edge of the data signal. Therefore, the relation between the phase error &thgr;
e
in a phase-locked loop which utilizes the above-mentioned phase detector and the voltage Vd can be adjusted to be nearly linear dependent, a phase-locked loop without dead zone thus can be derived. Furthermore, clock jitter can be reduced and tolerance for data random jitter can be improved.
To achieve the aforementioned objects, the present invention provides a phase detector, comprising N phase detection units: U
0
, U
1
, . . . , U
N−1
, (N is even, N≧4) connected in cascade configuration. Each phase detection unit U
j
(0≦j≦N−1) comprises an inverter, a first D flip-flop, an exclusive OR gate and a second D flip-flop. The inverter receives a clock signal CK
j
. The first D flip-flop receives a common data signal data at its data input terminal and the output signal of the inverter at its inverting clock input terminal. The exclusive OR gate receives the output signal of the first D flip-flop and another input signal. The second D flip-flop receives the output signal of the exclusive OR gate at its data input terminal and the clock signal CK
j
at its inverting clock input terminal, and outputs a charge/discharge signal. The another input signal of the exclusive OR gate in the phase detection unit U
j
(0≦j≦N−1) is the output signal of the first D flip-flop in the phase detection unit U
j+1(mod N)
. The phase difference between the clock signal CK
j
(0≦j<N−1) and CK
j+1
is 2&pgr;/N.
By using the phase detector in accordance with the present invention, the relation between the phase error &thgr;
e
in the phase-locked loop and the voltage Vd can be adjusted to be nearly linear by employing those control signals. Therefore, a phase-locked loop without dead zone can be derived, which can reduce clock jitter and improve the tolerance for data random jitter.


REFERENCES:
patent: 5592519 (1997-01-01), Honaker

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