Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase
Reexamination Certificate
2000-06-05
2001-05-01
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By phase
Reexamination Certificate
active
06225831
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to phase detectors generally and, more particularly, to a linear phase-detector used as in an analog phase-locked loop for data and clock recovery.
BACKGROUND OF THE INVENTION
Phase-detectors are logic circuits used to generate “pump-up” and “pump-down” signals to control a charge-pump circuit in a clock and data recovery PLL. Phase-detectors are also used to generate recovered data. As the operating speed of clock and data recovery circuits increases, the design of voltage-controlled oscillators (VCOs) becomes more complicated. High speed VCOs also consume more power.
Conventional phase-detector architectures use a full-rate clock. Some conventional architectures use multiple phases of a lower-rate clock but have non-linear characteristics or reduced linear range.
Referring to
FIG. 1
, a circuit
10
illustrating a conventional approach for implementing a phase-detector based on a “full-rate” clock is shown. A full-rate clock is defined as a clock signal having a frequency (measured in Hertz) that is numerically equal to the data rate (measured in bits/second). The circuit
10
comprises a flip-flop
12
, a flip-flop
14
, an XOR gate
16
and an XOR gate
18
. The XOR gate
16
generates a “pump-up” signal in response to a signal DATA and clocked-data input. The clocked-data input is generated by the flip-flop
12
in response to the signal DATA. The XOR gate
18
generates a “pump-down” signal using the output of the flip-flops
12
and
14
. The circuit
10
illustrates a phase-detector having linear phase-difference vs. gain characteristics.
The circuit
10
requires a full-rate clock which is more difficult to generate than a slower rate clock. In a PLL application, such a phase-detector would require a VCO (not shown) to run at the full-rate. As a result, the VCO would consume more power and would be more difficult to design than a VCO running at a slower rate.
Referring to
FIG. 2
, a circuit
30
illustrating a second approach for implementing a phase detector is shown. The circuit
30
generally comprises a latch
32
, a latch
34
, an AND gate
36
, an XOR gate
38
, a NAND gate
40
and a NAND gate
42
. The circuit
30
illustrates one of “n” parallel structures in an “n” bit parallel phase detector. The XOR gate
38
presents the pump-up signal PUn and the NAND gate
42
presents the pump-down signal PDn. The pump-down signal PDn is generated in response to the pump-up signal PUn through the latch
34
.
The circuit
30
relies on pump-up signal PUn for the generation of the pump-down signal PDn. As the phase-difference between the clock and the signal DATA decreases, the pump-up signal PUn becomes narrower and may fail to trigger the pump-down latch
34
, which may cause the pump-down signal PDn not to trigger in some applications. As a result, a non-linear operation may occur.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a pump-up circuit and a pump-down circuit. The pump-up circuit may be configured to generate a pump-up signal in response to (i) a data signal and a clock signal. The pump-down circuit may be configured to generate a pump-down signal in response to (i) the data signal, (ii) the clock signal, and (iii) a quadrature of the clock signal.
The objects, features and advantages of the present invention include providing a phase detector that (i) may operate at a reduced clock rate, (ii) may generate a pump-up signal independently of a pump-down signal, (iii) may reduce the power dissipated in high speed clock and data recovery circuits, (iv) may provide a linear output, (v) does not require full-rate clock signals to generate the pump-up and pump-down signals, and (vi) generates the pump-up and pump-down signals separately, allowing better control over the linearity characteristics of the gain curve.
REFERENCES:
patent: 4535459 (1985-08-01), Hogge, Jr.
patent: 5138281 (1992-08-01), Boudewijns
patent: 5301196 (1994-04-01), Ewen et al.
patent: 5384551 (1995-01-01), Kennedy et al.
patent: 5436938 (1995-07-01), Pigeon
patent: 5614855 (1997-03-01), Lee et al.
patent: 5754080 (1998-05-01), Chen et al.
patent: 5808498 (1998-09-01), Donnelly et al.
patent: 5825209 (1998-10-01), Stark et al.
patent: 5834950 (1998-11-01), Co et al.
patent: 5926041 (1999-07-01), Duffy et al.
patent: 5933031 (1999-08-01), Konno
patent: 5936430 (1999-08-01), Patterson
patent: 5939901 (1999-08-01), Geddes
patent: 5955906 (1999-09-01), Yamaguchi
patent: 5963058 (1999-10-01), Thomas
patent: 5963059 (1999-10-01), Partovi et al.
patent: 5977801 (1999-11-01), Boerstler
patent: 6014042 (2000-01-01), Nguyen
patent: 6026134 (2000-02-01), Duffy et al.
patent: 6064235 (2000-05-01), Hayashi et al.
patent: 6075388 (2000-06-01), Dalmia
patent: 6100722 (2000-08-01), Dalmia
A 0.8-&mgr;m CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links, By: Chih-Kong Ken Yang and Mark A. Horowitz, IEEE Journal of Solid-State Circuits, vol. 31, No. 12, Dec. 1996, pp. 2015-2023.
FP 15.3: A 1.25Gb/s, 460mW CMOS Transceiver for Serial Data Communication, By: Dao-Long Chen, Michael O. Baker, 1997 IEEE International Solid-State Circuits Conference, pp. 242-243.
FP 15.1: A 1.0625Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-Emphasis, By: Alan Fiedler, Ross Mactaggart, James Welch, Shoba Krishnan, 1997 IEEE International Solid-State Circuits Conference, pp. 238-239.
Kamal Dalmia, U.S.S.N. 09/302,214, Clock and Data Recovery PLL Based on Parallel Architecture, filed Apr. 29, 1999.
Kamal Dalmia, U.S.S.N. 09/302,213, Phase Detector with Extended Linear Range, filed Apr. 29, 1999.
Kamal Dalmia, U.S.S.N. 09/283,058, Method, Architecture and Circuit for Half-Rate Clock and/or Data Recovery, filed Apr. 1, 1999.
Dalmia Kamal
Navabi Mohammad J.
Williams Bertrand J.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Nuton My-Trang
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