Phase detection circuit

Details Phase detection circuit Phase detection circuit

2000-11-22

2002-04-23

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

C327S007000

Reexamination Certificate

active

06377081

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a phase detection circuit for the purpose of generating a local clock in accordance with the phase difference between two clock signals.
2. Related Art
In the past, to a phase detection circuit, for example, a signal comprising a random binary-coded stream generated by a clock of frequency f
0
, inputted and the phase detection circuit was used to generate a local clock with both a phase and a frequency synchronized to this clock signal.
For example, the first example of a phase detection circuit according to prior art, shown in
FIG. 9
, is formed by D-type flip-flops F/F
1
, F/F
2
, AND circuits AND
1
and AND
2
, an adder circuit ADD, and a delay circuit DL
1
. In a phase detection circuit configured in this manner, a first clock signal C
1
and a data signal D
1
are input, and output signals PDOUT and Q
2
are output.
With a phase detection circuit having the configuration of the first example of prior art, the timing of the clock C
1
input to the flip-flops F/F
1
and F/F
2
is the same. Thus, the timing of the signal Q
1
input to the flip-flop F/F
2
is delayed by a prescribed delay time tpd
1
.
In the above-noted phase detection circuit of the past, however, there was a need for a further increase in speed. With respect to this need, with the above-noted configuration of the past, the high the signal speed becomes, the more significant becomes the delay time tpd
1
of the flip-flop F/F
1
, thereby reducing the operation margin of the flip-flop F/F
2
. For this reason, depending upon the operating conditions and variations in the manufacturing conditions of the circuit, if the delay time tpd
1
changes, there is a further reduction in the operating margin, thereby leading to the problem of faulty operation.
For example, in the case of a 10-Gb/s NRZ signal, with a clock period T of 100 ps, the delay time tpd
1
is approximately 20 to 40 ps, and when the variations in various conditions are considered, the delay time tpd
1
becomes approximately 60 ps.
Accordingly, it is an object of the present invention to provide a phase detection circuit that enables the achievement of a sufficient operating margin.
SUMMARY OF THE INVENTION
In order to achieve the above noted objects, the present invention adopts the following basic technical constitution.
Specifically, the first aspect of the present invention is a phase detection circuit which detects a phase difference between a data signal D
1
and a clock signal C
1
, the detection circuit comprising: a first D-type flip-flop circuit F/F
1
, to which the data signal D
1
and the clock signal C
1
are input; a first delay circuit DL
2
which delays the clock signal C
1
by a prescribed amount of time, so as to generate a delayed clock signal C
1
′; a second D-type flip-flop circuit F/F
2
, to which an output signal Q
1
of the first D-type flip-flop circuit F/F
1
and the delayed clock signal C
1
′ are input; a second delay circuit DL
1
which delays the output signal Q
2
of the second D-type flip-flop circuit F/F
2
so as to generate a first delayed signal Q
2
′, a third delay circuit DL
3
which delay the an output signal Q
1
of the first D-type flip-flop circuit F/F
1
so as to generate a second delayed signal Q
1
′, a fourth delay circuit DL
4
which delays the data signal D
1
so as to generate a delayed data signal D
1
′, a first AND circuit AND
2
which calculates a logical product of the first delayed signal Q
2
′ and the second delayed signal Q
1
′ so as to output a DOWN signal, a second AND circuit AND
1
which calculates a logical product of the second delayed signal Q
1
′ and the delayed data signal D
1
′ so as to output an UP signal, and an adder circuit ADD which adds the UP signal and the DOWN signal so as to output a detection signal PDOUT detecting the phase difference between the data signal D
1
and the clock signal C
1
.
In the second aspect of the present invention, the first D-type flip-flop circuit F/F
1
operates at rising edge of the clock signal C
1
and the second D-type flip-flop circuit F/F
2
operates at a falling edge of the delayed clock signal C
1
′.
In the third aspect of the present invention, to the first AND circuit, the second delayed signal and an inverted signal of the first delayed signal are input, and to the second AND circuit, the delayed data signal and an inverted signal of the second delayed signal are input
The fourth aspect of the present invention is a phase detection circuit which detects a phase difference between a data signal D
1
and a clock signal C
1
, the detection circuit comprising: a first D-type flip-flop circuit F/F
1
, to which the data signal D
1
and the clock signal C
1
are input; a first delay circuit DL
12
which delays the clock signal C
1
by a prescribed amount of time, so as to generate a delayed clock signal C
1
′; a second D-type flip-flop circuit F/F
2
, to which an output signal Q
1
of the first D-type flip-flop circuit F/F
1
and the delayed clock signal C
1
′are input; a second delay circuit DL
13
which delays the an output signal Q
1
of the first D-type flip-flop circuit F/F
1
so as to generate a first delayed signal Q
1
′, a third delay circuit DL
11
which delays the data signal D
1
so as to generate a second delayed signal D
1
′, a first exclusive-OR circuit XOR
2
which calculates a logical product of an output signal Q
2
of the second D-type flip-flop circuit F/F
2
and the first delayed signal Q
1
′ so as to output a DOWN signal, a second exclusive-OR circuit XOR
1
which calculates a logical product of the first delayed signal Q
1
′ and the second delayed signal D
1
′ so as to output an UP signal, and an adder circuit ADD which adds the UP signal and the DOWN signal so as to output a detection signal PDOUT detecting the phase difference between the data signal and the clock signal.


REFERENCES:
patent: 5015970 (1991-05-01), Williams et al.
patent: 6034554 (2000-03-01), Francis et al.
patent: 63-60650 (1988-03-01), None
patent: 7-131448 (1995-05-01), None
patent: 11-112335 (1999-04-01), None

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