Phase-detecting device

Details Phase-detecting device Phase-detecting device

2001-11-21

2003-08-05

Oda, Christine (Department: 2858)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

Frequency of cyclic current or voltage

C324S076520

Reexamination Certificate

active

06603300

ABSTRACT:

This application incorporates by reference Taiwanese application Serial No. 90100656, filed on Jan. 11, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The invention relates in general to a detecting device, and more particularly to a phase-detecting device for a delay locked loop (DLL).
2. Description of related art
In order to meet design requirements, signals are delayed in logic circuits. Of various designs of delay circuits, delay locked loop can accurately delay input signals by ¼, ½ or one cycle to meet different requirements for different circuit designs.
FIG. 1
illustrates phase relationship between a reference signal and a delay signal. As shown, the reference signal S is a typical square wave, and the delay signal SD lags the reference signal S by ¼ cycle (T/4). Therefore, the delay signal SD and the reference signal S have the same waveform, but their phases are different by T/4.
FIG. 2
illustrates a block diagram of a delay locked loop. The delay locked loop includes a delay circuit
210
, a phase detector
220
and a counter
230
, and is used for delaying a reference signal
20
. As shown, the delay circuit
210
has the reference signal
20
as input, and determines a delay time based upon a counting signal
23
from the counter
230
. Namely, different delay times for the reference signal
20
can be made by different counting signals
23
. For example, if the counting signal
23
is 0, the delay time generated by the delay circuit
210
is shortest. By gradually increasing the value of the counting signal
23
, the delay time is increased gradually, resulting in the time delay of the reference signal
20
.
To further improve the accuracy of the time delay, a feedback loop is implemented. Practically, the counting signal
23
is set to 0 at the beginning such that the reference signal
20
is delayed by a shortest delay time. The delayed reference signal
20
is feedback to the phase detector
220
for detecting a phase difference between the reference signal
20
and the feedback signal
25
. Accordingly, the phase detector
220
can determine whether the delay time for the reference signal
20
satisfies the design requirements. According to the detected result, the phase detector
220
feeds a delay control signal
22
into the counter
230
so that the value of the counting signal
23
is increased. The counting signal
23
is then fed into the delay circuit
210
so as to increase the delay time of the reference signal
20
. As the delay time is increased, the delayed reference signal
20
is further feedback to the phase detector
220
. The delay time is continuously adjusted until the delay circuit
210
generates a required delay time. Therefore, the required delay time for the reference signal
20
can be obtained.
In addition, with the circuit structure based on the circuit in
FIG. 2
, an approach to the obtaining of a signal at a frequency of 100 MHz with a delay time of ¼ cycle is described as follows. That is, a signal with a delay time of 2.5 ns is to be generated according to the approach described above.
FIG. 3
shows a block diagram of the delay locked loop. First, a reference signal
30
with a frequency of 200 MHz is used for delaying and adjusting. The reference signal
30
is inverted to a reference signal
30
a
by an inversion logic circuit
310
, and then the inverted reference signal
30
a
is feedback to the phase detector
220
. Through a buffer
320
, a feedback signal
35
is buffered as a feedback signal
35
a
and then feedback to the phase detector
220
. According to a phase difference between the feedback signal
35
a
and the reference signal
30
a,
the phase detector
220
generates a delay control signal
32
and outputs it to the counter
230
for adjusting a delay time for the reference signal
30
until the delay circuit
210
generates a correct delay time. Since the process has been explained previously, the detailed description will not be made for the sake of brevity. A timing diagram is shown next for further describing timing relationship among the signals.
FIG. 4
shows a timing diagram of the reference signal and the feedback signal in FIG.
3
. Referring
FIGS. 3 and 4
, the reference signal
30
a
and the feedback signal
35
a
are inputted to the phase detector
220
at the same time. Because the feedback signal
35
is generated by delaying the reference signal
30
through the delay circuit
210
, the phase of the feedback signal
35
a
lags behind the phase of the reference signal
30
a,
assuming the response times for both of the inversion logic circuit
310
and the buffer
320
are equal. The phase detector
220
captures the level (voltage amplitude) of the feedback signal
35
a
at the rising edge r
0
of the reference signal
30
a.
For the waveforms shown in
FIG. 4
, the feedback signal
35
a
captured is a logic “1”. By proper design, the delay control signal
32
can be set to a logic “1” when the phase detector
220
captures a logic “1” signal. The delay control signal
32
is inputted to the counter
230
to increase the counting value of the counting signal
33
; thereby, the delay time for the reference signal is extended. Accordingly, the phase difference between the feedback signal
35
a
and the reference signal
30
a
is increased as the delay time for the reference signal
30
is increased. According to the phase difference between the feedback signal
35
a
and the reference signal
30
a,
the rising edge r
5
of the feedback signal
35
a
is shifted to right. Next, the phase detector
220
further detects the level of the feedback signal
35
a
at the rising edge r
0
of the reference signal
30
a.
If the captured signal is in a logic “1” state, the delay control signal
32
is set to the logic “1” state again to increase the counting value of the counting signal
33
, whereby the delay time for the reference signal
30
is further delayed. Therefore, the phase difference between the feedback signal
35
a
and the reference signal
30
a
is increased further. Namely, the rising edge r
5
of the feedback signal
35
a
is shifted to right further. Accordingly, by the control scheme above, once the rising edge of the reference signal
30
a
is detected to be the logic “1” state, the delay time for the reference signal
30
is increased further and the feedback signal
35
is lagged behind the reference signal
30
.
As the foregoing description, the rising edge of the feedback signal is gradually shifted to right as the delay time for the reference signal is gradually increased. As the rising edge of the feedback signal is further shifted to right until the rising edge r
5
′ (shown in
FIG. 4
) slightly lags behind the rising edge r
0
, the signal detected at the rising edge r
0
is a logic “0” instead of logic “1”. By proper design, when the signal with the logic “0” state detected by the phase detector
220
, the delay control signal
32
can be set to logic “0”. The counting value of the counting signal
33
is then decreased so that the delay time generated by the delay circuit
210
is decreased. As a result, the rising edge r
5
leads the rising edge r
0
so that the delay control signal
32
becomes logic “1” and the counting value of the counting signal
33
is increased. By repeating the foregoing process, the rising edges r
0
and r
5
are kept within a very short interval. As shown, the rising edges r
0
and r
5
′ are apart by about ½ cycle.
According to the foregoing description, the delay time can be fixed at about ½ cycle (T/2) by the delay locked loop. Namely, when the frequency of the reference signal
30
is 200 MHz, the delay time is 2.5 ns. It should be noted that according to the original purpose it intends to delay a signal with a frequency of 100 MHz by T/4. However, in practice, the reference signal
30
with a frequency of 200 MHz is delayed to obtain a delay time of 2.5 ns. Once the delay time is determined, the delay time of 2.5 ns is equivalent to the case when a signal with a frequency of 100

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