Electric power conversion systems – Current conversion – With means to introduce or eliminate frequency components
Reexamination Certificate
2000-11-09
2003-03-04
Patel, Rajnikant B. (Department: 2838)
Electric power conversion systems
Current conversion
With means to introduce or eliminate frequency components
C318S811000
Reexamination Certificate
active
06529393
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to three-phase voltage-source inverters, and more particularly relates to a method and apparatus for sensing phase current with shunt resistors on inverter legs.
BACKGROUND OF THE INVENTION
Pulse width modulation (PWM) techniques are used to control three-phase (3&phgr;) voltage-source inverters (VSI), in applications such as control of DC brushless, AC induction motors, permanent-magnet synchronous motors, and other 3&phgr; loads. For example, PWM inverters make it possible to control both the frequency and magnitude of the voltage and current applied to a motor. As a result, PWM inverter-powered motor drives offer better efficiency and higher performance compared to fixed frequency motor drives. The energy that a PWM inverter delivers to a load is controlled by PWM signals applied to the gate or base of the power transistors.
Several PWM techniques are known and used in the art, for determining the modulating signal and the switch-on/switch-off instants from the modulating signal. Currently popular examples are sinusoidal PWM, hysteric PWM, and space-vector (SV) PWM. These techniques are commonly used for control of AC induction, BLDC and switched reluctance (SR) motors.
PWM can be either symmetric, or asymmetric, as shown in FIG.
1
. In
FIG. 1
two pulse waveforms
10
and
12
, are shown for four contiguous, equal periods. The top waveform
10
in the figure is an example of an asymmetric PWM, in which the timing for the leading edge in each period varies, as shown by arrow
14
, while the trailing edge always coincides with the end of the period. The bottom waveform
12
in the figure is an example of a symmetric PWM, in which the timing for both the leading edge and the trailing edge is varied by the same amount in opposite directions, as shown by arrows
16
and
18
, respectively, resulting in symmetry for the waveform in every period.
A circuit diagram of a typical 3&phgr; VSI
20
is shown in
FIG. 2. A
DC voltage, V
DC
, is provided between a V
+
BUS
22
and a V
−
BUS
24
. Three legs are connected between bus
22
and bus
24
. The first leg includes a power transistor Q
1
having its collector connected to bus
22
, and a power transistor Q
2
having its collector connected to the emitter of transistor Q
1
and having its emitter connected to bus
24
. A diode D
1
is connected between the emitter and collector of transistor Q
1
, and a diode D
2
is connected between the emitter and collector of transistor Q
2
. In both cases the cathode of the diode is connected to the collector of the transistor. A control signal a is provided on line
26
to the base of transistor Q
1
, while a control signal a′ is provided on line
28
to the base of transistor Q
2
. The common connection point of transistors Q
1
and Q
2
is connected to line
38
, which carries the output voltage V
a
and phase a current i
a
of the first leg.
The other two legs are of the same structure as the first leg. Thus, the second leg includes a power transistor Q
3
having its collector connected to bus
22
, and a power transistor Q
4
having its collector connected to the emitter of transistor Q
3
and having its emitter connected to bus
24
. A diode D
3
is connected between the emitter and collector of transistor Q
3
, and a diode D
4
is connected between the emitter and collector of transistor Q
4
. In both cases the cathode of the diode is connected to the collector of the transistor. A control signal b is provided on line
30
to the base of transistor Q
3
, while a control signal b′ is provided on line
32
to the base of transistor Q
4
. The common connection point of transistors Q
3
and Q
4
is connected to line
40
, which carries the output voltage V
b
and phase b current i
b
of the second leg.
Similarly, the third leg includes a power transistor Q
5
having its collector connected to bus
22
, and a power transistor Q
6
having its collector connected to the emitter of transistor Q
5
and having its emitter connected to bus
24
. A diode D
5
is connected between the emitter and collector of transistor Q
5
, and a diode D
6
is connected between the emitter and collector of transistor Q
6
. In both cases the cathode of the diode is connected to the collector of the transistor. A control signal c is provided on line
34
to the base of transistor Q
5
, while a control signal c′ is provided on line
36
to the base of transistor Q
6
. The common connection point of transistors Q
5
and Q
6
is connected to line
42
, which carries the output voltage V
c
and phase c current i
c
of the third leg.
In operation, when an upper transistor, Q
1
, Q
3
or Q
5
, is turned on, i.e., when a, b or c is 1, the corresponding lower transistor, Q
2
, Q
4
, or Q
5
, is switched off, i.e., the corresponding a′, b′ or c′ is 0. The on and off states of the upper transistors are sufficient to evaluate the output voltage for the purposes of this discussion. The relationship between the switching variable vector [a, b, c], the line-to-line output voltage vector [V
ab
V
bc
V
ca
] and the phase (line-to-neutral) output voltage vector [V
an
V
bn
V
cn
], for a balanced load, is given by the following equations:
[
V
ab
V
bc
V
ca
]
=
[
1
-
1
0
0
1
-
1
-
1
0
1
]
[
a
b
c
]
Equation (1)
[
V
bn
V
bn
V
cn
]
=
[
2
-
1
-
1
-
1
2
-
1
-
1
-
1
2
]
[
a
b
c
]
Equation (2)
where V
DC
is the DC supply voltage, or the bus voltage.
There are eight possible combinations of on and off states for the three upper power transistors. The eight combinations and the derived output line-to-line and phase voltages in terms of DC supply voltage V
DC
, according to Equation (1) and Equation (2), are shown in Table 1:
TABLE 1
a
b
c
V
an
V
bn
V
cn
V
ab
V
bc
V
ca
0
0
0
0
0
0
0
0
0
1
0
0
2/3
−1/3
−1/3
1
0
−1
1
1
0
1/3
1/3
−2/3
0
1
−1
0
1
0
−1/3
2/3
−1/3
−1
1
0
0
1
1
−2/3
1/3
1/3
−1
0
1
0
0
1
−1/3
−1/3
2/3
0
−1
1
1
0
1
1/3
−2/3
1/3
1
−1
0
1
1
1
0
0
0
0
0
0
Assume d and q are the fixed horizontal and vertical axes in the plane of the three motor phases. The vector representations of the phase voltage corresponding to the eight combinations can be obtained by applying the following so-called d-q transformation to the phase voltages:
T
abc
-
dq
=
2
3
[
1
-
1
2
-
1
2
0
3
2
-
3
2
]
Equation
(
3
)
This transformation is equivalent to an orthogonal projection of [a,b,c] onto the two dimensional plane having perpendicular axes d axis
50
and q axis
52
, perpendicular to the vector [
1
,
1
,
1
] in a three-dimensional coordinate system, the results of which are six non-zero vectors and two zero vectors as shown in FIG.
3
. The six non-zero vectors form the axes of a hexagonal
54
having six sectors
56
,
58
,
60
,
62
,
64
and
66
, each bounded by two of the non-zero vectors. The angle between any adjacent two non-zero vectors is 60 degrees. The zero vectors are at the origin of axes
50
,
52
, and apply zero voltage to the three-phase load. The eight vectors are called the basic space vectors and are denoted in
FIG. 3
by U
0
, U
60
, U
120
, U
180
, U
240
, U
300
, O
000
, and O
111
.
The same d-q transformation can be applied to a desired three-phase voltage output to obtain a desired reference voltage vector u
out
in the d-q plane as shown in FIG.
3
. In general, the vector u
out
has a magnitude of ∥u
out
∥ and an angle of &agr; with respect to one of the two basic vectors forming the sector that contains u
out
in an instant of time. Being in the sector
56
bounded by space vectors U
0
and U
60
, the particular vector u
out
shown in
FIG. 3
may be expressed as the vector sum of two vector components u
1
and u
2
, having the same angle as space vectors U
0
and U
60
, respectively. Note that t
Brady III W. James
Moore J. Dennis
Patel Rajnikant B.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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