Phase correcting DPSK/PSK receiver with digitally stored phase c

Details Phase correcting DPSK/PSK receiver with digitally stored phase c Phase correcting DPSK/PSK receiver with digitally stored phase c

1988-05-06

1989-12-19

Griffin, Robert L.

Pulse or digital communications

Repeaters

Testing

375 83, 329306, H03D 322

Patent

active

048887935

ABSTRACT:
A received phases modulated signal includes a plurality of information bits preceeded by three preamble bits. At periodic time intervals, approximately equal to one bit period, the receiver samples the signal and determines the phase angle of each bit at the sampling time. For the preamble bits, the receiver computes the phase error between the first and second preamble bits (A.sub.y -A.sub.x) and the phase error between the second and third preamble bits (A.sub.z -A.sub.y). An overall phase error (PE) is computed by taking the average of these two phase errors. To demodulate a DPSK signal, the average phase error (PE) is added to the phase angle (A.sub.i) of the present information bit. This adjusted phase angle (A.sub.i ') is then compared to the phase angle of the previous bit (A.sub.i -1) to demodulate the signal. To demodulate a PSK signal, the average phase error (PE) multiplied by D is added to the phase angle of the present information bit. This adjusted phase angle (A.sub.i ') is compared to the phase angle (A.sub.r) of a reference bit to demodulate the signal. D is the "distance"; i.e., the number of bits between the present information bit and reference bit.

REFERENCES:
patent: 3675139 (1972-07-01), Guest
patent: 4715047 (1987-12-01), Hambley
patent: 4746872 (1988-05-01), Yamagata

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