Oscillators – Ring oscillators
Reexamination Certificate
2001-06-22
2003-09-09
Mis, David C. (Department: 2817)
Oscillators
Ring oscillators
C331S034000, C331S172000, C331S17700V
Reexamination Certificate
active
06617936
ABSTRACT:
BACKGROUND OF THE INVENTION
Communication circuits use clock multipliers to convert a lower frequency reference clock, rclk, to a higher frequency bit clock, bclk. For example, the preferred embodiment uses a clock multiplier to convert a 156 MHz reference clock to a 1.248 GHz bit clock, a multiplication factor of eight. As described in pending patent application Ser. No. 09/557,640, filed Apr. 25, 2000, prior art communication systems have employed phase-locked loops (PLLs) and delay-locked loops (DLLs) to perform clock multiplication. PLL clock multipliers suffer from increased jitter because they integrate phase error over many reference clock cycles, and DLL-based clock multipliers introduce jitter due to device mismatch. The above referenced application shows how a multiplying-DLL-based clock multiplier can be used to give low jitter by eliminating both of these effects.
SUMMARY OF THE INVENTION
The present invention relates to improvements in an oscillator circuit by which its phase is controlled and to particular applications of the improved oscillator circuit.
In accordance with one aspect of the invention, an input signal has a frequency about equal to or less than the resonant frequency of an oscillator. A coupler couples the input signals to an oscillating signal in the oscillator to cause a phase shift of the oscillating signal toward the phase of the input signal.
In certain embodiments, the resonant frequency of the oscillator is about equal to an integer multiple of the frequency of input signal. The input signal has a pulse duration less than or equal to a pulse duration of the oscillating signal. The oscillating signal may be gated by the input signal to stop the oscillator, or the coupler may provide soft phase correction in which each active edge of the input signal moves the phase of the oscillating signal only part of the distance needed to align it with the input signal. The input signal may comprise a reference clock and a delayed version of the reference clock and may be generated in a pulse generator from a reference clock.
In certain embodiments, the frequency of the input signal is about equal to the resonant frequency. The oscillator may amplify the input signal. The oscillator may filter the input signal such as to filter pulse width variations of the input signal. When combined with an input oscillator which generates the input signal from a reference clock, the oscillator circuit may filter jitter from the reference clock. The coupler may provide a filtering time constant which is greater than a cycle time of the input signal.
In phase interpolator embodiments of the invention, at least one input signal is selectively coupled with at least one oscillating signal. Injection signals of multiple phases may be selectively coupled to an oscillating signal of the oscillator, or an input signal may be selectively coupled to oscillating signals of multiple phases. The coupler may comprise N digitally adjustable resistors coupled to N oscillating signal phases. In certain embodiments, at most two resistors couple the input signal at any one time. A conductance of the resistors is varied to interpolate between phases. The resistors may, for example, comprise NFETs, segmented NFETs, transmission gates or segmented transmission gates.
In certain embodiments, a free running frequency of the oscillator is controlled by a reference delay. A free running frequency of the oscillator may be controlled by a phase comparator or a replica oscillator. The replica oscillator may be controlled by a phase locked loop or a delay locked loop.
The oscillator may be a ring oscillator and may be a differential oscillator. In certain embodiments, the ring oscillator comprises inverter delay elements. The oscillator may include plural stages such as two or three stages, and they may include source coupled stages. The oscillator may be an LC oscillator.
The coupler may comprise a partial NAND gate or a partial NOR gate. The coupler may comprise a conductance between phases of a ring oscillator. The conductance may, for example, be an FET or a transmission gate. The coupler may comprise an inverter or a resistor.
REFERENCES:
patent: 5563554 (1996-10-01), Mizuno
patent: 5708381 (1998-01-01), Higashisaka
patent: 6025756 (2000-02-01), Miyabe
patent: 6188291 (2001-02-01), Gopinathan et al.
patent: 6317008 (2001-11-01), Gabara
Rategh, Hamid R., et al., “Superharmonic Injection Locked Oscillators as Low Power Frequency Dividers,” 1998 Sympos. on VLSI Circuits Digest of Tech. Papers, pp. 132-135 (1998).
Rategh, Hamid R., et al., “Superharmonic Injection-Locked Frequency Dividers,”IEEE Journal of Solid-State Circuits, 34(6) : 813-821 (Jun. 1999).
Wong, K. W., et al., “Phase Tuning Beyond 180 Degrees by Injection-Locked Oscillators,IEEE Tencon '93/Beijing”, pp. 1-4 (1933).
Wong, L. W., et al., “Frequency Synthesis Using Non-Integral Subharmonic Injection Locking,” IEEETencon'93, pp. 16-19 (1993).
Tokumitsu, Tsuneo, et al., A Novel Injection-Locked Oscillator MMIC with Combined Ultrawide-Band Active Combiner/Divider and Amplifiers,IEEE Trans. on Microwave Theory and Tech., 42(12) :2572-2578 (1994).
Dally William J.
Farjad-Rad Ramin
Greer, III Thomas H.
Ng Hiok-Tiaq
Poulton John W.
Hamilton Brook Smith & Reynolds P.C.
Mis David C.
Velio Communications, Inc.
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