Electric power conversion systems – Current conversion – Including d.c.-a.c.-d.c. converter
Reexamination Certificate
2001-09-27
2002-10-29
Berhane, Adolf Deneke (Department: 2838)
Electric power conversion systems
Current conversion
Including d.c.-a.c.-d.c. converter
C363S056020
Reexamination Certificate
active
06473316
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a phase control circuit appropriately used in a resonant switching regulator, etc. which adopts soft switching so as to reduce switching loss, and the resonant switching regulator provided with the phase control circuit.
BACKGROUND OF THE INVENTION
Conventionally, as for a phase control circuit for a switching regulator, a structure disclosed in U.S. Pat. No. 5,291,384 (Date of Patent: Mar. 1, 1994) has been known. A phase control circuit disclosed in the patent is structured so as to control a pulse width modulation (PWM) circuit which controls the phases of output signals A and B and output signals C and D, using an output pulse of an oscillation circuit.
FIG. 6
shows a block diagram of the conventional phase control circuit. In
FIG. 6
, an output of a switching circuit
53
is switched by a clock signal
52
outputted from an oscillator
51
.
Output signals XA
54
and XB
55
of the switching circuit
53
have opposite polarities, and are inputted to output circuits A
56
and B
57
, respectively. Delay circuits
56
A and
57
A are provided in the output circuits A
56
and B
57
, respectively, and a delay period of each of the delay circuits
56
A and
57
A is set by a delay set AB
58
. Each of the delay circuits
56
A and
57
A causes a delay in the rising timing of an output signal A
59
outputted from the output circuit A
56
, and in the rising timing of an output signal B
510
outputted from the output circuit B
57
.
The output signal XA
54
of the switching circuit
53
is also connected to a first input terminal
512
of an XOR circuit
511
. To a second input terminal
513
of the XOR circuit (exclusive OR)
511
, a signal from an output terminal of a PWM latch circuit
514
is provided.
The XOR circuit
511
outputs output signals XC
515
and XD
516
, and these output signals are inputted to output circuits C
517
and D
518
, respectively. The output signals XC
515
and XD
516
have opposite polarities, in the same way as the foregoing output signals XA
54
and XB
55
.
The output circuits C
517
and D
518
include delay circuits
517
A and
518
A, respectively, in the same way as the output circuits A
56
and B
57
. A delay is caused in the rising timing of an output signal C
520
outputted from the output circuit C
517
, and in the rising timing of an output signal D
521
outputted from the output circuit D
518
, by a delay period set by a delay set CD
519
.
In an error amplification circuit
522
, a first reference voltage source
524
is connected to a positive input terminal
523
, and a monitor signal voltage
526
is inputted to a negative input terminal
525
. The voltages at the positive input terminal
523
and at the negative input terminal
525
are compared and their difference is amplified to form an error signal
527
, which is inputted to two comparators
528
and
538
.
To a positive input terminal
529
of the PWM comparator
528
, one of the comparators, the error signal
527
, which is an output signal of the error amplification circuit
522
, is inputted. To a negative input terminal
530
of the PWM comparator
528
, a ramp wave signal
532
formed according to the clock signal
52
is inputted via a level shift circuit
531
. The PWM comparator
528
compares the foregoing two signals and outputs a first error detection signal
533
.
The first error detection signal
533
is inputted to a set terminal
534
of the PWM latch circuit
514
as an input signal only when the clock signal
52
is in a low level. In such a set input, the polarity of each of the output signals C
520
and D
521
is reversed, compared with the case where the PWM latch circuit
514
is in a reset state.
The PWM latch circuit
514
, once set, keeps the output low until being reset by the clock signal
52
. Besides, in the PWM latch circuit
514
, while a signal is inputted to a reset terminal
535
, no signal is applied to the set terminal
534
, and the output of the PWM latch circuit
514
is always in a high level.
Another comparator
538
, to which the error signal
527
as an output of the error amplification circuit
522
is inputted, compares a voltage level of the error signal
527
and a voltage level (for example, 1V) of a second reference voltage source
536
. When the voltage level of the error signal
527
is lower than the voltage level of the second reference voltage source
536
, the comparator
538
outputs a second error detection signal
537
(in a high level).
The second error detection signal
537
has a function to apply no signal according to the clock signal
52
to the reset terminal
535
of the PWM latch circuit
514
. Hence, when the second error detection signal
537
is outputted, if a signal is inputted to the set terminal
534
of the PWM latch circuit
514
even just once, the output of the PWM latch circuit
514
is kept low unless the second error detection signal
537
is cancelled (becomes low).
FIG. 7
shows a resonant switching regulator which controls regulator output voltage using the phase control circuit shown in FIG.
6
.
FIG. 8
shows a timing chart of the circuit shown in FIG.
7
.
The output signals A
59
, B
510
, C
520
, and D
521
of the phase control circuit are inputted as control signals for switches A
639
, B
640
, C
641
, and D
642
, respectively, of the resonant switching regulator. Here, the switches A
639
and D
642
, and the switches B
640
and C
641
are paired respectively so as to transmit a current through a primary
643
and supply power to a secondary
644
of a transformer
650
.
When this phase control circuit is used as a controller for the resonant switching regulator, the first reference voltage source
524
is connected to the positive input terminal
523
of the error amplification circuit
522
. To the negative input terminal
525
of the error amplification circuit
522
, the monitor signal voltage
526
, formed by dividing the voltage of a regulator output terminal
648
to which power is supplied from the secondary
644
of the transformer
650
, is supplied.
Here, in order to make the voltages inputted to the both input terminals of the error amplification circuit
522
equal, the phase control circuit controls the switching phases of the paired switches A
639
, B
640
, C
641
, and D
642
. Then, the phase control circuit adjusts power supply to the secondary
644
of the transformer
650
, so that the voltage of the regulator output terminal
648
comes to have a desired voltage level set by the error amplification circuit
522
, and thus a feedback control is applied in a system.
When the voltage level of the monitor signal voltage
526
is much lower than the reference voltage of the first reference voltage source
524
of the error amplification circuit
522
, no high signal is applied to the set terminal
534
of the PWM latch circuit
514
. Therefore, the output of the PWM latch circuit
514
becomes high. Here, the output signals of the paired output circuits have the same polarity, and the switching phases of the paired switches in the resonant switching regulator become 0 degree. Under these conditions, power is supplied to the secondary
644
of the transformer
650
, except during dead time, which is a delay period.
When the voltage level of the monitor signal voltage
526
is much higher than the reference voltage of the first reference voltage source
524
of the error amplification circuit
522
, the second error detection signal
537
is outputted. So no high signal is applied to the reset terminal
535
of the PWM latch circuit
514
, and if a signal in a high level is inputted to the set terminal
534
even just once during this period, the output of the PWM latch circuit
514
becomes low. Here, the output signals of the paired output circuits come to have opposite polarities, and the switching phases of the paired switches in the resonant switching regulator become 180 degrees. In this situation, power is not supplied to the secondary
644
of the transformer
650
.
When the vo
Fujiyama Toshiya
Inamori Masanori
Berhane Adolf Deneke
Sharp Kabushiki Kaisha
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