Wave transmission lines and networks – Plural channel systems – Having branched circuits
Reexamination Certificate
2001-02-07
2003-01-07
Pascal, Robert (Department: 2817)
Wave transmission lines and networks
Plural channel systems
Having branched circuits
C327S308000
Reexamination Certificate
active
06504449
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a switched attenuator for selectively attenuating high frequency signals. More particularly, the present invention relates to a switched attenuator which maintains linearity across a wide frequency range.
2. Description of the Related Art
Due to parasitic capacitance, a Gallium-Arsenide (GaAs) FET will present a decreasing isolation as a function of frequency when turned off. This is illustrated by the solid line in
FIG. 1
which shows a typical S
21
isolation response of a GaAs FET in an off state.
FIG. 1
also shows a dotted line representing the typical insertion loss of a GaAs FET in an on state.
Due to the isolation characteristics, just one GaAs FET is not typically used in a switched 20 dB pad which is intended to function up to 3 GHz. In the on state, a single GaAs FET can have an insertion loss lower than −1 dB at 3 GHz. Such a low insertion loss, as illustrated in
FIG. 1
, which is associated with the low on state return loss, is not identified as being provided in FET attenuators advertised by current manufacturers.
FIG. 2
shows a prior art switched attenuator which includes two GaAs FET's to form the switches
2
and
4
.
SUMMARY OF THE INVENTION
In accordance with the present invention, a phase compensated switched attenuation device is provided for attenuating high frequency signals. In one embodiment, a through-path GaAs FET is coupled between input and output ports for switching the device between a through state and an attenuation state. First and second isolation FET's are coupled to the input port and output port, respectively for isolating the through-path FET from a pad coupled to the isolation FET's. A resistor or a series combination of a resistor and capacitor can be coupled to the first and second isolation FET's in parallel with the pad. Resistors are provided for coupling gates of the FET's to a plurality of voltage sources. A device in accordance with one embodiment of the present invention can maintain an insertion loss of less than 1 dB for frequencies up to 3 GHz.
REFERENCES:
patent: 4890077 (1989-12-01), Sun
patent: 5049841 (1991-09-01), Cooper et al.
Barber Richard G.
Constantine Cornelius
Anritsu Company
Fliesler Dubb Meyer & Lovejoy LLP
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