Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural a.f.s. for a single oscillator
Reexamination Certificate
2003-03-26
2004-10-26
Shingleton, Michael B (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Plural a.f.s. for a single oscillator
C331S016000, C331S025000, C331S175000, C331S17700V, C331S17700V, C327S156000, C327S159000
Reexamination Certificate
active
06809597
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to phase comparison methods and/or circuits, and phase locked loop (PLL) type circuits, and more particularly to a phase comparison method and/or circuit, and phase locked loop (PLL) type circuit that can control the capacitance of varactors, or the like, in a voltage controlled oscillator (VCO).
BACKGROUND OF THE INVENTION
A phase locked loop (PLL) circuit typically includes a phase comparison circuit that can receive an input signal and feedback signal by way of a feedback loop. The feedback serves to adjust a frequency of the feedback signal to match that of the input signal. PLL circuits enjoy a wide variety of applications in various fields.
A PLL circuit can be considered “locked” when the phase comparison circuit indicates essentially no phase difference between the input signal and feedback signal, and/or when the phases of the input signal and feedback signal match one another, and maintain such a phase match.
A phase difference between an input signal and a feedback signal is detected by a phase comparison circuit. Such a phase difference can be translated into a voltage and applied to a variable capacitance element (a varactor), which may form part of resonator within a voltage controlled oscillator (VCO) in a later stage of the PLL circuit. A varactor provides a capacitance that varies in accordance with an applied voltage. Thus, in the above PLL arrangement, a varactor capacitance can reflect the phase difference between the input signal and the feedback signal.
A conventional technique that includes a phase comparison circuit for controlling a varactor is disclosed in U.S. Pat. No. 6,150,891 (hereinafter the '891 patent). The '891 patent shows a technique in which a plurality of signals are generated with a shift register, and such signals are applied to corresponding phase comparison circuits.
FIG. 8
shows a conventional PLL circuit like that described in the '891 patent. In
FIG. 8
, a conventional PLL circuit includes a shift register circuit
200
, a phase comparison circuit
201
, a voltage controlled oscillator (VCO)
202
, a frequency divider
203
having a frequency division ratio of N (an N-frequency divider), a frequency divider
204
having a frequency division ratio of Q (a Q-frequency divider), and a frequency divider
205
having a frequency division ratio of R (an R-frequency divider).
In the conventional arrangement of
FIG. 8
, a shift register
200
receives a signal SET as an input that is generated by frequency dividing an output signal f
out
by “N” within N-frequency divider
203
. Shift register
200
may also receive a signal CLKQ at a clock input that is generated by frequency dividing an output signal f
OUT
by “Q” within Q-frequency divider
204
. Shift register
200
may then output a number of predetermined signal SIGi (where i=0 to M) that are provided to phase comparison circuit
201
.
Phase comparison circuit
201
includes M+1 phase difference detection circuits
210
. Each of the phase detection circuits
210
receives as inputs, one of the signals SIGi and a reference signal REF. A reference signal REF is generated by frequency dividing an input reference signal f
REF
by “R” within R-frequency divider
205
. Each phase detection circuit
210
can output a voltage signal to the VCO
202
that corresponds to a detected phase difference between their respective input signal SIGi and reference signal REF. A VCO
202
can change capacitance values of varactors of a resonator according to voltage signals received from phase detection circuits
210
. Such changes in varactor capacitance values can control the oscillation frequency of output signal f
OUT
. The PLL circuit of
FIG. 8
can be considered locked when the frequency of output signal f
OUT
matches that of reference signal f
REF
.
FIG. 9
sets forth a timing chart that illustrates the operation of a phase comparison circuit
201
.
FIG. 10
is a diagram illustrating the configuration of a phase difference detection circuit
210
. The operation of a phase comparison circuit
201
will now be described with reference to
FIGS. 8
,
9
and
10
. As noted above, a conventional phase comparison circuit
201
can include “0−M” phase difference detection circuit
210
. Thus, if M=2, a phase comparison circuit
201
includes three phase difference signals that receive signals SIGi as inputs (where i=0 to M), respectively.
Referring to
FIG. 10
, conventional phase difference detection circuit
210
can receive a signal SIG
0
as an input. A conventional phase difference detection circuit
210
includes a voltage source V
nom
for generating a predetermined initial potential, a logical sum circuit AND
0
, capacitors C
0
a
and C
0
b
, a resistor R
0
, and three switches SW
0
a
, SW
0
b
, and SW
0
c
. It is understood that switches SW
0
a
, SW
0
b
and SW
0
c
are operated to not close at the same time. In addition, an output node N
0
can be connected to a capacitor C
0
a
, and provide an output voltage to a VCO. Each of the
0
-M phase difference detection circuits
210
receiving a signal SIGi can have the same general configuration as that of
FIG. 10
, except for the particular input signal received.
A shift register
200
receives as inputs the signals CLKQ and SET. The signal CLKQ is obtained by frequency-dividing output signal f
out
by Q and the signal SET is obtained by frequency dividing output signal f
out
by N. According to such input signals, shift register
200
generates signals SIGi as outputs. Frequency division ratios N and Q of frequency dividers
203
and
204
, respectively, are set to meet the relationship N>Q. Thus, the cycle of signal CLKQ can be shorter than that of signal SET. Further, signals SIGi generated by shift register
200
rise concurrently with the rise of signal SET and fall later than the fall of signal SET by i cycles of the signal CLKQ, respectively. Thus, signals SIGi have the timing as set forth in FIG.
9
.
While a signal SET is at a high level, a phase difference detector
210
supplies the potential of capacitor C
0
b
to capacitor C
0
a
by way of switch SW
0
a
. Such a potential can represent a phase detection result for a previous cycle. In this way, a potential corresponding to a phase detection operation can be presented at node N
0
.
Switch SW
0
b
may then close to charge capacitor C
0
b
with an initial potential Vnom. In this way an initial potential can be established on capacitor C
0
b.
Upon the fall of a signal SET, an AND gate AND
0
may close according to the logical combination of the signal REF and SIG
0
. That is, switch SW
0
c
will close in the time period that signals REF and SIG
0
are both high. If switch SW
0
c
is closed, electric charge from capacitor C
0
b
will discharge to ground through resistor R
0
. Thus, the initial potential of capacitor C
0
b
can be discharged for a time period corresponding to a phase difference between the signal REF and SIG
0
. In this way, a potential corresponding to a phase difference can be established on capacitor C
0
b.
In the particular example of
FIG. 9
, the signal SIG
0
falls before the rise of signal REF. Thus, there is no period time after the signal SET falls during which signals REF and SIG
0
are both high. Consequently, switch SW
0
c
remains open, and essentially no charge on capacitor C
0
b
is discharged through resistor R
0
.
From the above description it is understood that each phase difference detection circuit
210
closes a switch SWic (where i=0−M) for a period of time corresponding to a phase difference between one of the signals SIGi and REF. In particular, each phase difference detection circuit can detect the time between the rise of signal REF and the fall of signal SIGi, and discharge a capacitor Cib during such a time period. As noted previously, the potential established across capacitor Cib is supplied to corresponding capacitor Cia when signal SET rises once again to a high level.
FIG. 11
shows changes in voltage due to a disc
NEC Electronics Corporation
Sako Bradley T.
Shingleton Michael B
Walker Darryl G.
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