Phase comparator using digital and analogue phase detectors

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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328155, 307262, 307511, 331 25, H03K 906, H03D 1300

Patent

active

051051605

ABSTRACT:
A digital phase detector circuit has an up/down counter for counting clock pulses (CPS) to determine the number of clock pulses that occur in the time interval between opposite edges of a first signal (VSC) and one edge of a reference signal (PL) synchronized with the clock pulses (CPS). A latch provides a first digital output signal (DES) which represents the number. The phase detector also has an analogue phase detector circuit having a flip-flop for producing a second signal (VCS') which corresponds to the first signal (VCS) and is synchronized with the clock pulses (CPS). Logic gates and determine the time intervals between corresponding edges of the first and second signals (VCS,VCS'), and a circuit element determines a phase error voltage (VS) from these time intervals. The voltage (VS) is digitized to provide a second digital output signal (AES). The first and second digital output signals (DES,AES) are combined to produce a resultant digital output signal (DPE) which represents an overall indication of phase difference.

REFERENCES:
patent: 4107623 (1978-08-01), Graf et al.
patent: 4246497 (1981-01-01), Lawson et al.
patent: 4523150 (1985-06-01), Hogeboom
patent: 4639680 (1987-01-01), Nelson
patent: 4772843 (1988-09-01), Asaka et al.
patent: 4884040 (1989-11-01), Fling
IBM Technical Disclosure Bulletin, "Variable Frequency Oscillator Using A Frequency Discriminator", J. W. Rae and D. P. Swart, vol. 27, No. 1A, Jun. 1984.

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