Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase
Reexamination Certificate
2000-10-26
2002-12-17
Callahan, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By phase
C327S007000, C327S012000, C327S156000, C331S017000
Reexamination Certificate
active
06496042
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase comparator provided in a phase locked loop (referred to as a PLL hereinafter) used for extracting a clock signal that identifies and regenerates a non-return-to-zero (NRZ) receiving signal in a receiving circuit for use in transmitting a digital signal.
2. Description of the Related Art
The following literature are available which describe the conventional techniques relating to the above field.
Publication (1): Dan H. Wolaver, “Phase-Locked Loop Circuit Design”, 1991, PTR Prentice Hall, Prentice Hall, Inc., A Paramount Communications Company, Englewood Cliffs, N.J. 07632, P. 222
Publication (2): Vincent von Kaenel, Daniel Aebischer, Christian Piguet and Evert Dijkstra, “A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generation”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 31 [11] (US), 1996, PP. 1715-1722
FIG. 1
shows a structure of a general PLL circuit.
This PLL circuit includes a phase comparator
10
which detects a phase difference between data Si having a phase of &thgr;i(t) and an output signal So having a phase of &thgr;o(t), and which generates an output voltage Vp proportional to the detected phase difference. A loop filter
30
is connected to an output terminal of the phase comparator
10
, and an output terminal of the loop filter
30
is connected to a voltage controlled oscillator (referred to as VCO hereinafter)
32
. The loop filter
30
is a circuit which smoothes out the output voltage Vp and extracts a control voltage Vc: proportional to the phase difference. The loop filter includes, for example, a low-pass filter having a resistor R and capacitor C. The VCO
32
is a circuit in which the oscillation frequency is controlled by the control voltage Vc output from the loop filter
30
so as to output the output signal So having the phase of &thgr;o. This output signal So is fed back to the phase comparator
10
.
In the PLL circuit, the response mode and the response speed are determined by a characteristic of the loop filter
30
. In the closed-loop operation of the PLL circuit, in order to seek a stable state (locked state) such that the difference between the phase &thgr;i(t) of the input data Si and the phase &thgr;o(t) of the output signal So becomes constant (that is, &thgr;i(t)−&thgr;o(t)=constant), the phase &thgr;o(t) of the output signal So automatically approaches that of the output signal Si. If there is no input data Si, the control voltage Vc output from the loop filter
30
is 0, so that the VCO
32
oscillates at a free running frequency fo. When the data Si having the frequency fi is inputted, the phases of the frequency fi and the frequency fo are compared by the phase comparator
10
. Then, the output voltage Vp corresponding to the phase difference is inputted to the loop-filter
30
and applied to a control terminal of the VCO
32
, so that the phase difference is controlled so as to be a constant value. When the oscillating frequency fo of the VCO is sufficiently close to the frequency fi of the data Si, the frequency fo will be locked to the frequency fi, so that the phase difference becomes constant and there will be no frequency difference.
FIG. 2
is a circuit diagram of the phase comparator described in the publication (1) and shown in FIG.
1
.
The comparator includes an input terminal
11
which inputs data Si, and an input terminal
12
which inputs the output signal So from the VCO
32
. An inverter
13
which inverts the output signal So is connected to the input terminal
12
. Delayed flip-flop circuits (referred to as D-FF hereinbelow)
14
and
15
are connected to the input terminal
11
and the inverter
13
, respectively. 2-input exclusive OR gates (referred to as EXOR hereinafter)
16
and
17
are connected to the output sides of the D-FF
14
and
15
, respectively.
The D-FF
14
includes a data input terminal D connected to input terminal
11
, a clock input terminal CK connected to the input terminal
12
, and an output terminal Q outputting the data. The D-FF
14
is a circuit which detects the data Si inputted to the data input terminal D at a positive edge (rising edge) of the output signal So inputted from the clock input terminal CK and stores the inputted data Si. The output terminal Q of the D-FF
14
is connected to one of the input terminals of the EXOR gate
16
. The D-FF
15
includes a data input terminal D connected to the output terminal Q of the D-FF
14
, a clock input terminal CK which inputs an inverted signal obtained after the output signal So was inverted by the inverter
13
, and an output terminal Q outputting the data. The D-FF
15
is a circuit which detects the output signal of the D-FF
14
at a positive edge of the inverted signal of the output signal So inputted to the clock input terminal CK and stores such the output signal of the D-FF
14
. This output terminal Q of the D-FF
15
is connected to one of input terminals of the EXOR gate
17
.
The EXOR gate
16
is a circuit which takes the EXOR of the data Si inputted to the two input terminals and the output signal of the D-FF
14
, so as to output the output signal S
18
from the output terminal
18
. The EXOR gate
17
is a circuit which takes the EXOR of the output signal of the D-FF
14
inputted to the two input terminals and the output signal of the D-FF
15
, so as to output the output signal S
19
from the output terminal
19
. The output terminals of the EXOR gates
16
and
17
are connected to the output terminals
18
and
19
, respectively.
FIGS. 3A through 3C
are timing charts showing the operation of the phase comparator shown in FIG.
2
.
FIG. 3A
is a timing chart where the phase of the data Si matches that of the VCO output signal So.
FIG. 3B
is a timing chart where the phase of the VCO output signal So is delayed compared to that of the data Si.
FIG. 3C
is a timing chart where the phase of the VCO output signal So is ahead of that of the data Si. Next, the operation of the phase comparator shown in
FIG. 2
will be described with reference to
FIGS. 3A-3C
.
For example, let us consider a case where the data Si repeat in a sequence of 0, 1, 0, 1, . . .
Referring to
FIG. 3A
where the phase of the data Si matches that of the VCO output signal So, the output terminals
18
and
19
are outputted by repeating the pulses of the same pulse width (output signals S
18
and S
19
) alternately at the period of the VCO signal So.
Referring to
FIG. 3B
where the phase of the VCO output signal So is delayed compared to that of the data Si, the output terminal
18
generates a pulse (output signal S
18
) having a pulse width broader by the phase-delay amount.
Referring to
FIG. 3C
where the phase of the VCO output signal So is ahead of that of the data Si, the output terminal
18
generates a pulse (output signal S
18
) having a pulse width narrower by the amount by which the phase is ahead. Thus, the difference between the time average of the output signal S
18
and the time average of the output signal S
19
becomes a value proportional to the phase difference in the range of −&pgr; to +&pgr;, so as to carry out the operation of the phase comparator.
Moreover, when the data Si are a sequence of 0, 0, 0, . . . or 1, 1, 1, . . . , the output signals S
18
and S
19
become 0. Thus, in the case where the data Si having the same repeated values are inputted in a continuous manner as above, the phase comparator outputs biased output signals S
18
and S
19
, so as to be able to prevent jitter in the PLL circuit. In this manner, the phase comparator can be used in the PLL circuit for use in extracting the clock signal that identifies and regenerates the receiving signal from the NRZ-signal data Si.
FIG. 4
shows a conceptual diagram of the conventional charge pump provided at the output side.
This charge pump is a circuit which calculates the time average of the pulses in the output signal S
18
and S
19
outputted from the output terminals
18
and
19
in the phase comparator shown
Burdett James R.
Callahan Terry D.
Luu An T.
Oki Electric Industry Co. Ltd.
Venable Baetjer Howard & Civiletti LLP
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