Phase comparator circuit for high speed signals in delay...

Details Phase comparator circuit for high speed signals in delay... Phase comparator circuit for high speed signals in delay...

1997-06-04

2001-02-27

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

C327S147000, C327S107000, C331S025000, C375S375000

Reexamination Certificate

active

06194916

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase comparator and a semiconductor integrated circuit, and more particularly, to a phase comparator for a delay locked loop (DLL) circuit and a semiconductor integrated circuit employing the DLL circuit.
2. Description of the Related Art
Recently, the operating speeds of semiconductor integrated circuits have increased, and the circuit scale thereof has become large. Further, it has become necessary to supply a synchronized signal (phase synchronized clock signal) to a specific circuit in a large scale semiconductor integrated circuit.
Namely, recent high-speed, highly-integrated semiconductor circuits need phase-synchronized clock signals. For example, synchronous DRAMs (SDRAMs) employ a DLL (Delay Locked Loop) circuit that generates an internal clock signal in synchronization with an externally supplied clock signal and supplies the internal clock signal to output buffer circuits. As the frequency of the external clock signal increases, a phase difference between the external and internal clock signals increases. Even if the frequency of the external clock signal is high, the DLL circuit must correctly compare the phases of the external and internal clock signals with each other and synchronize the internal clock signal with the external clock signal.
Recent MPUs and memory devices such as SDRAMs operate at a speed of 100 MHz or faster. These devices employ the DLL circuit to lock the phase of an internal clock signal with that of an externally supplied clock signal, to thereby absorb a delay caused by internal clock lines and stabilize an accessing time.
When the frequencies of the external and internal clock signals are high, it is difficult for the DLL circuit to compare the phases of the signals with each other. To cope with this problem, a prior art has proposed a phase locked loop (PLL) circuit that divides the frequencies of the external and internal clock signals at a given ratio and compares the phases of the frequency-divided clock signals with each other. This technique is disclosed in, for example, Japanese Unexamined Patent Publication (Kokai) Nos. 55-92042 and 56-61833.
The conventional PLL circuit and related DLL circuit and the problems thereof will be explained later in detail with reference to drawings.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a phase comparator capable of correctly comparing the phases of high-speed clock signals with each other and applicable to a DLL circuit that operates on high-speed clock signals. Another object of the present invention is to provide a semiconductor integrated circuit that employs such a DLL circuit.
According to the present invention, there is provided a phase comparator for comparing phases of first and second signals with each other, comprising a first control circuit for dividing a frequency of the first signal by n in response to a third signal where n is an integer equal to or larger than 2; a second control circuit for dividing a frequency of the second signal by n in response to the third signal; and a phase comparator for comparing phases of signals provided by the first and second control circuits with each other.
The phase comparator may be incorporated in a DLL circuit so that the DLL circuit determines a delay according to a phase comparison result provided by the phase comparator.
Further, according to the present invention, there is also provided a semiconductor integrated circuit having a delay circuit for delaying a first signal and providing a second signal, a delay control circuit for controlling a delay of the delay circuit, and a phase comparator for comparing phases of the first and second signals with each other and controlling an operation of the delay control circuit accordingly, wherein the phase comparator comprises a first control circuit for dividing a frequency of the first signal by n in response to a third signal where n is an integer equal to or larger than 2; a second control circuit for dividing a frequency of the second signal by n in response to the third signal; and a phase comparator for comparing phases of signals provided by the first and second control circuits with each other.
Each period of a signal provided by any one of the first and second control circuits may comprise a first-level interval corresponding to Y periods of any one of the first and second signals and a second-level interval corresponding to Z periods of any one of the first and second signals where Y and Z are positive integers, respectively. The phase comparator may have a first RS flip-flop and a second RS flip-flop; the first RS flip-flop having a reset terminal to receive the signal provided by the first control circuit and a set terminal to receive the signal provided by the second control circuit, the second RS flip-flop having a reset terminal to receive the signal provided by the first control circuit through a delay circuit and a set terminal to receive the signal provided by the second control circuit, and the first and second RS flip-flops providing output signals whose combination is used to determine a phase comparison result.
Each of the first and second RS flip-flops may have a first NAND circuit and a second NAND circuit, the first NAND circuit having a first input serving as the reset terminal of the RS flip-flop and a second input connected to an output of the second NAND circuit serving as an output terminal of the RS flip-flop, the second NAND circuit having a first input serving as the set terminal of the RS flip-flop and a second input connected to an output of the first NAND circuit serving as an inverting output terminal of the RS flip-flop. Each of the NAND circuits may have a first p-channel transistor, a second p-channel transistor, a first n-channel transistor, and a second n-channel transistor; the first p-channel transistor having a source connected to a first power source line, a drain connected to the output of the NAND circuit, and a gate connected to the first input of the NAND circuit; the second p-channel transistor having a source connected to the first power source line, a drain connected to the output of the NAND circuit, and a gate connected to the second input of the NAND circuit; the first n-channel transistor having a source connected to the drain of the second n-channel transistor, a drain connected to the output of the NAND circuit, and a gate connected to the first input of the NAND circuit; and the second n-channel transistor having a source connected to a second power source line and a gate connected to the second input of the NAND circuit.
The semiconductor integrated circuit may further comprise a frequency divider for forming the third signal by dividing a signal, which has the same period as the first signal, by n. The semiconductor integrated circuit may further comprise a circuit for shifting the first signal by &tgr;/N where &tgr; is a delay of the second signal from the first signal and N is a positive integer and forming the third signal by dividing a frequency of the shifted signal by n with the use of the frequency divider.
A frequency dividing ratio of the first and second signals to be divided at the same timing may be ½
m
where m is a positive integer. Each of the first and second control circuits may have a first latch circuit for storing the third signal in response to a trigger signal that is an inversion of a corresponding one of the first and second signals, and a second latch circuit for storing signals held in the first latch circuit in response to a trigger signal that is the corresponding one of the first and second signals.
The semiconductor integrated circuit may comprise a first DLL circuit made of the above described semiconductor integrated circuit, a second DLL circuit, and an objective circuit, and one of output signals of the first and second DLL circuits may be selected and supplied to the objective circuit. The semiconductor integrated circuit may be a synchronous DRAM and the objective circuit may

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