Phase comparator and synchronizing signal extracting device

Details Phase comparator and synchronizing signal extracting device Phase comparator and synchronizing signal extracting device

2001-05-18

2003-10-14

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

C327S020000, C327S156000, C331S025000, C331SDIG002, C375S376000

Reexamination Certificate

active

06633184

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase comparator employed in the data communication system, etc. and a synchronizing signal extracting device using the same and, more particularly, a phase comparator which can be synchronized with not only the continuous repetitive pulse but also the discontinuous data pulse with missing pulses since the omission of pulses is caused like the tooth missing and a synchronizing signal extracting device using the same.
2. Description of the Related Art
In the data communication, the data pulse train being sent must be interpreted without error to decode the original signal precisely. For this purpose, the synchronizing signal must be detected from the data pulse train being sent, and then the original signal must be decoded by using this synchronizing signal. In order to detect the synchronizing signal, the frequency and the phase must be caused to coincide with those of the received pulse train. In the prior art, the phase locked loop (referred to as a “PLL” hereinafter) circuit shown in
FIG. 1
is normally employed as such detecting means.
A PLL circuit
150
shown in
FIG. 1
comprises the phase comparator
151
having a comparing function for comparing a phase of the input pulse with a phase of the clock signal to output a voltage signal in accordance with the compared result and a frequency discriminating function, etc., as occasion demands, the low-frequency filter/amplifier
152
for extracting a low-frequency component by removing a high-frequency component in the voltage signal output from the phase comparator
151
, and the voltage-controlled oscillator
153
for oscillating at a frequency, that responds to the voltage signal containing only the low-frequency component being output from the low-frequency filter/amplifier
152
, to generate the clock signal. In this PLL circuit
150
, when the phase of the clock signal being output from the voltage-controlled oscillator
153
lags behind the phase of the input pulse, the phase comparator
151
detects this lag and also increases the voltage signal in accordance with this detected result to increase the frequency of the clock signal being output from the voltage-controlled oscillator
153
and to advance the phase of the clock signal. In contrast, when the phase of the clock signal being output from the voltage-controlled oscillator
153
goes ahead of the phase of the input pulse, the phase comparator
151
detects this lead and also decreases the voltage signal in accordance with this detected result to lower the frequency of the clock signal being output from the voltage-controlled oscillator
153
and to delay the phase of the clock signal.
When the continuously repetitive pulse is input, this PLL circuit
150
can relatively easily cause to coincide the phase of the clock signal being output from the voltage-controlled oscillator
153
with the phase of the input pulse. Therefore, this PLL circuit
150
is extensively employed in the frequency synthesizer, etc.
However, according to the phase comparator
151
constituting such PLL circuit
150
, the special regard must be paid to the discontinuous pulse train with missing pulses like the tooth missing caused in the data communication when the pulse train is modulated by the data. Therefore, such PLL circuit
150
cannot attain the sufficient function and the sufficient performance as the PLL circuit.
For this reason, in the prior art, as shown in
FIG. 2
, the phase comparator
159
was developed (Dan H. Wolaver. Phase Locked Loop Circuit Design, p.202, Prentice Hall. ISEN 0-13-662743-9) as the phase comparator that can be applied to such discontinuous pulse train with missing pulses. This phase comparator
159
comprises two D flip-flop circuits
154
,
155
, one inverter circuit
156
, and two exclusive-OR circuits
157
,
158
, and is able to directly execute the phase comparison of the discontinuous pulse train, e.g., the NRZ (Non Return to Zero)-modulated pulse.
Also, as shown in
FIG. 3
, the phase comparator
168
was also developed (Dan H. Wolaver, Phase Locked Loop Circuit Design, p.221, Prentice Hall, ISBN 0-13-662743-9). This phase comparator
168
comprises two D flip-flop circuits
160
,
161
, two exclusive-OR circuits
162
,
163
, and four resistors
164
,
165
,
166
,
167
, and is able to execute the phase comparison of the RZ(Return to Zero)-modulated pulse which can be obtained by previously differentiating the NRZ-modulated pulse.
FIG. 4
shows an outline of the PLL circuit
191
that employs the phase comparator
171
like the phase comparator
159
as the phase comparator
151
, and the charge pump unit
172
as the low-frequency filter/amplifier
152
. In this case, since the phase comparator
168
has the output waveform and the operation almost identical to those of the phase comparator
159
, explanation of the PLL circuit employing this phase comparator
168
will be omitted herein.
The phase comparator
191
shown in
FIG. 4
comprises the phase comparator
171
for comparing the frequency and the phase of the discontinuous pulse train Data input into the input terminal
169
with those of the clock signal Xck
1
input into the input terminal
170
and also generating pulses W, X in accordance with this compared result; the charge pump unit
172
for increasing the voltage value of the voltage signal by executing the charging operation when the pulse W is output from this phase comparator
171
and also decreasing the voltage value of the voltage signal by executing the discharging operation when the pulse X is output from this phase comparator
171
; and the voltage-controlled oscillator
173
for increasing the oscillating frequency as the voltage value of the voltage signal being output from this charge pump unit
172
is increased higher and also decreasing the oscillating frequency as the voltage value of the voltage signal being output from this charge pump unit
172
is decreased lower so as to generate the clock pulse Xck
1
. This phase comparator
191
controls the oscillating frequency of the voltage-controlled oscillator
173
such that the minimum pulse width of the discontinuous input pulse train Data can coincide with the repetitive period of the clock signal Xck
1
, and generates the clock signal Xck
1
whose frequency is twice the maximum repetitive frequency of the discontinuous pulse train Data.
The phase comparator
171
comprises the D flip-flop circuit
174
for acquiring the pulse train Data input into the data input terminal D when the clock signal Xck
1
input into the input terminal
170
rises and then outputting this pulse train Data from the output terminal Q while holding such pulse train Data; the inverter circuit
175
for inverting the clock signal Xck
1
input into the input terminal the D flip-flop circuit
176
for acquiring the pulse train Data output from the output terminal Q of the D flip-flop circuit
174
from the data input terminal p when the inverted signal of the clock signal Xck
1
output from this inverter circuit
175
rises and then outputting this pulse train Data from the output terminal Q while holding such pulse train Data; the exclusive-OR circuit
177
for calculating the exclusive-OR between the discontinuous pulse train Data input into the input terminal
169
and the pulse train Data output from the D flip-flop circuit
174
to generate the pulse W; and the exclusive-OR circuit
178
for calculating the exclusive-OR between the pulse train Data output from the D flip-flop circuit
174
and the pulse train Data output from the delayed flip-flop circuit
176
to generate the pulse X.
Then, as shown in (b) of
FIG. 5
, when the clock signal Xck
1
input into the input terminal
170
rises, the D flip-flop circuit
174
is caused to acquire the pulse train Data, shown in (a) of
FIG. 5
, that is input into the input terminal
169
and to hold this pulse train Data. When the clock signal Xck
1
input into the input terminal
170
falls and the inverted signal of the clock signal Xck
1
output fr

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