Phase comparator and process for the operation thereof

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307355, 328159, 307361, 307205, 328109, 328133, H03K 520

Patent

active

040398595

ABSTRACT:
A phase comparator has at least two signal comparison inputs and at least one resistance line and one or more voltage amplitude comparators. A first comparator input of each voltage amplitude comparator is connected to the resistance line. One end of the resistance line is connected by way of a first dc voltage blocking means to the first signal comparison input and the second signal comparison input is connected by way of an inverter and a second dc voltage blocking means to the other end of the resistance line. In one mode of operation the one end of the resistance line is connected to a fixed voltage and the other end is connected to an impressed current source, and the second comparator inputs of all the voltage amplitude comparators are connected to a fixed reference voltage which is equal to the arithmetic mean of the two voltages present at the ends of the resistance line and produced by the current source and the voltage source. In this mode of operation each signal comparison input is fed with one of two input signals which are to be compared and the output signal of the phase comparator is provided in parallel from all of the comparator outputs. In another mode of operation, one end of the resistance line is connected to a fixed voltage and the other end is connected to an impressed current source. The second comparator input of all the voltage amplitude comparators are connected to a fixed reference voltage which is equal to the arithmetic mean of the two voltages present at the ends of the resistance line and produced by the fixed voltage and the impressed current source. The two ends of a second resistance line are connected to a fixed voltage and a further resistor has one end connected to a tap of the second resistance line and another end connected to a fixed voltage. In this mode of operation each signal comparison input is fed, in each case, with one of the two input signals which are to be compared and the output signal of the phase comparator is obtained at the tap of the second resistance line.

REFERENCES:
patent: 3021481 (1962-02-01), Kalmus
patent: 3458721 (1969-07-01), Maynard
patent: 3478227 (1969-11-01), Ito
patent: 3743946 (1973-07-01), Gass et al.
patent: 3761740 (1973-09-01), Naive
IBM Tech Disclosure Bul. vol. 9, No. 12, May 1967, "Self-Decoding Comparator Circuit", by Woodman, p. 1797.

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