Phase comparator accurately comparing phases of two clock...

Details Phase comparator accurately comparing phases of two clock... Phase comparator accurately comparing phases of two clock...

2002-06-03

2004-03-02

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

C327S158000, C331S025000, C331S00100A, C375S376000

Reexamination Certificate

active

06700414

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase comparator and a clock generation circuit employing the phase comparator. More specifically, the present invention relates to a phase comparator comparing phases of first and second clock signals and to a clock generation circuit generating a second clock signal in accordance with a first clock signal.
2. Description of the Background Art
FIGS. 13A and 13B
are time charts showing an operation principle of a conventional phase comparator. As shown in
FIG. 13A
, when a phase of a feedback clock signal FBCLK precedes a phase of an internal clock signal INTCLK, the feedback clock signal FBCLK is raised to the “H” level earlier than the internal clock signal INTCLK, so that the feedback clock signal FBCLK is at the “H” level when the internal clock signal INTCLK rises.
As shown in
FIG. 13B
, when a phase of a feedback clock signal FBCLK follows a phase of an internal clock signal INTCLK, the internal clock signal INTCLK is raised to the “H” level earlier than the feedback clock signal FBCLK, so that the feedback clock signal FBCLK is at the “L” level when the internal clock signal INTCLK rises.
A conventional phase comparator therefore detects a level of a feedback clock signal FBCLK in response to a rising edge of an internal clock signal INTCLK, and shows that a phase of the feedback clock signal FBCLK is preceding by setting signals &phgr;U and &phgr;D to the “H” level and the “L” level respectively if the feedback clock signal FBCLK is at the “H” level, and shows that a phase of the feedback clock signal FBCLK is delaying by setting signals &phgr;U and &phgr;D to the “L” level and the “H” level respectively if the feedback clock signal FBCLK is at the “L” level.
Therefore, it is possible to have a feedback clock signal FBCLK and an internal clock signal INTCLK in phase with each other by delaying the phase of the feedback clock signal FBCLK if the signals &phgr;U and &phgr;D are at the “H” level and the “L” level respectively, or by advancing the phase of the feedback clock signal FBCLK if the signals &phgr;U and &phgr;D are at the “L” level and the “H” level respectively.
Though the conventional phase comparator works well with an internal clock signal INTCLK and its delayed clock signal, i.e., a feedback clock signal FBCLK if they have the same waveforms, problems as follows will occur if the waveforms are different.
As shown in
FIG. 14A
, if a phase of a feedback clock signal FBCLK precedes a phase of an internal clock signal INTCLK while the rising of the feedback clock signal FBCLK is obtuse, the feedback clock signal FBCLK is at the “L” level when the internal clock signal INTCLK rises. As a result, the signals &phgr;U and &phgr;D will be at the “L” level and the “H” level respectively, so that the phase of the feedback clock signal FBCLK will further be advanced even though the phase of the feedback clock signal FBCLK is already preceding the phase of the internal clock signal INTCLK.
Furthermore, as shown in
FIG. 14B
, if an internal clock signal INTCLK and a feedback clock signal FBCLK are in phase while the duty ratio of the feedback clock signal FBCLK is above 50%, the feedback clock signal FBCLK is at the “H” level when the internal clock signal INTCLK rises. As a result, the signals &phgr;U and &phgr;D will be at the “H” level and the “L” level respectively, so that the phase of the feedback clock signal FBCLK will be advanced even though the internal clock signal INTCLK and the feedback clock signal FBCLK are in phase.
Furthermore, as shown in
FIG. 14C
, if an internal clock signal INTCLK and a feedback clock signal FBCLK are in phase while the duty ratio of the feedback clock signal FBCLK is below 50%, the feedback clock signal FBCLK is at the “L” level when the internal clock signal INTCLK rises. As a result, the signals &phgr;U and &phgr;D will be at the “L” level and the “H” level respectively, so that the phase of the feedback clock signal FBCLK will be delayed even though the internal clock signal INTCLK and the feedback clock signal FBCLK are in phase.
As mentioned above, the conventional phase comparator works well with an internal clock signal INTCLK and a feedback clock signal FBCLK having the same waveforms, while when the waveforms are different, it cannot accurately compare the phases of the internal clock signal INTCLK and the feedback clock signal FBCLK.
SUMMARY OF THE INVENTION
A main object of the present invention is to provide a phase comparator which can accurately compare phases of first and second clock signals and a clock generation circuit which employs the phase comparator.
A phase comparator according to the present invention includes a first level detection circuit detecting a level of a second clock signal in response to a rising edge of a first clock signal, a second level detection circuit detecting a level of a second clock signal in response to a falling edge of a first clock signal, a first logic circuit outputting a first signal indicating that the phase of the second clock signal precedes the phase of the first clock signal in response to the detection of the first and second levels by the first and second level detection circuits respectively, and a second logic circuit outputting a second signal indicating that the phase of the second clock signal follows the phase of the first clock signal in response to the detection of the second and the first levels by the first and second level detection circuits respectively.
Furthermore, a clock generation circuit according to the present invention includes a delay circuit delaying a first clock signal and generating a second clock signal, the delay circuit has a controllable delay time, a phase comparator comparing phases of the first and second clock signals, and a control circuit controlling the delay time of the delay circuit to have the first and second clock signals in phase with each other based on a comparison result of the phase comparator. The phase comparator includes a first level detection circuit detecting a level of a second clock signal in response to a rising edge of a first clock signal, a second level detection circuit detecting a level of a second clock signal in response to a falling edge of a first clock signal, a first logic circuit outputting a first signal indicating that the phase of the second clock signal precedes the phase of the first clock signal in response to the detection of the first and second levels by the first and second level detection circuits respectively, and a second logic circuit outputting a second signal indicating that the phase of the second clock signal follows the phase of the first clock signal in response to the detection of the second and the first levels by the first and second level detection circuits respectively.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 4764737 (1988-08-01), Kaatz
patent: 5142555 (1992-08-01), Whiteside
patent: 5233636 (1993-08-01), Lee et al.
patent: 5789947 (1998-08-01), Sato
patent: 6157690 (2000-12-01), Yoneda
patent: 6417715 (2002-07-01), Hamamoto et al.
patent: 5-110427 (1993-04-01), None
patent: 6-29835 (1994-02-01), None

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