Phase comparator

Details Phase comparator Phase comparator

1999-07-30

2001-04-17

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

C327S003000, C375S373000

Reexamination Certificate

active

06218868

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a phase comparator which is suitable for detecting small phase differences of high-speed pulses used in, for example, tracking correction of optical discs, by suppressing the influence of spike noises occurring in the signals as much as possible.
(2) Description of the Prior Art
Phase comparators have been used in various fields, such as PLL-circuits or various other fields in which a phase comparison result is used for control. The simplest way of configuring a phase comparator is direct use of an exclusive-OR (EX-OR). However, this configuration provides only the phase difference, without any information of phase lead and phase lag. To overcome this, Japanese Patent Application Laid-Open Hei 4 No.234226, proposed a comparator which outputs phase lead and phase lag, independently by detecting leading edges of pulses using flip-flops having an edge-triggered property, as shown in the circuit diagram of this publication.
FIG. 1
shows the circuit diagram of this conventional phase comparator.
FF
601
and FF
602
are leading-edge triggered D-type flip-flops while FF
603
and FF
604
are trailing-edge triggered D-type flip-flops. G
601
and G
602
are AND gates while G
603
and G
604
are NOR gates.
The D-inputs of all the flip-flops are connected to a power source. The clock inputs to FF
601
and FF
603
are connected to a lead-phase input terminal Inlead
6
while the clock inputs to FF
602
and FF
604
are lag-phase input terminal Inlag
6
. The reset inputs to FF
601
and FF
602
are connected to the output from G
601
while the reset inputs to FF
603
and FF
604
are connected to the output from G
602
. The inputs to G
601
are the outputs Q
601
and Q
602
from FF
601
and FF
602
, respectively. The inputs to G
602
are the outputs Q
603
and Q
604
from FF
603
and FF
604
, respectively. The inputs to G
603
are the outputs Q
601
and Q
603
from FF
601
and FF
603
, respectively. The inputs to G
604
are connected to the outputs Q
602
and Q
604
from FF
602
and FF
604
, respectively. The output from G
603
is connected to a phase lead output terminal OUTlead
6
while the output from G
604
is connected to a phase lag output terminal OUTlag
6
.
In the case where input signal Inlead
6
leads input signal Inlag
6
, upon first transitions (leading edge) of the input signals, the Q-output from FF
601
becomes ‘H’ during only the time (phase difference) between the two first transitions (leading edge). Upon second transitions (trailing edge) of the input signals, the Q-output from FF
603
becomes ‘H’ during only the time between the two second transitions (trailing edge). Similarly, in the case where input signal Inlead
6
lags behind input signal Inlag
6
, the Q-output from FF
602
becomes ‘H’ upon first transitions (leading edge) of the input signals and the Q-output from FF
604
becomes ‘H’ upon second transitions (trailing edge) of the input signals. Accordingly, when input signal Inlead
6
leads input signal Inlag
6
, output signal OUTlead
6
becomes ‘L’ during only the time of phase difference between two first transitions (leading edge) of the input signals and during only the time of phase difference between two second transitions (trailing edge) of them. When input signal Inlead
6
lags behind input signal Inlag
6
, output signal OUTlag
6
becomes ‘L’ during only the time of phase difference between two first transitions (leading edge) of the input signals and during only the time of phase difference between two second transitions (trailing edge) of them.
CMOS circuits need less current consumption, but produce the problem of a large signal delay. So, ECL circuits have been used in the fields where high-speed operations are needed, though the current consumption is high. A leading-edge triggered flip-flop is configured of six gates as shown in FIG.
2
. Therefore, the phase comparator shown in
FIG. 1
is composed of many gates, that is, twenty-four NAND gates, two AND gates and two NOR gates. If this phase comparator is constructed of ECL circuits, the current consumption for the whole circuit amounts to as much as the current for twenty-eight units of the gate driving current for one gate, so a considerably high current consumption is needed.
When flip-flops having an edge-triggered property are used, if a spike noise arises on the input signal to be edge triggered, it can readily cause malfunction because of the circuit's inherent features. Referring to the timing chart shown in
FIG. 3
, for example, If a spike noise
1
arises and is input to input terminal Inlag
6
during interval t
1
to t
2
, the positive logic, output pulse width PW
1
from Q
601
is shortened as shown in the chart (the output pulse width PW
2
from OUTlead
6
is also shortened). Since most phase difference comparators operate by integrating the output pulses, this will not cause fatal influence if a single pulse only is shorted in its pulse width by a spike noise.
However, if, for example, a spike noise
2
arises and input to input terminal Inlag
6
during interval t
4
to t
5
, there is a fear that the positive logic, output pulse width PW
3
from Q
602
might become markedly longer than the original pulse width PW as shown in the chart (the output pulse width PW
4
from OUTlag
6
also becomes long). In the case where the output is integrated, extremely long pulse widths as in this case produce an erroneous integral.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a phase comparator which can be configured with a fewer number of gates of ECL circuits, and which can operate with lower current consumption to achieve suitable detection of a small phase difference, by suppressing the influence of spike noises arising in the signals as much as possible.
In accordance with the first aspect of the invention, a phase comparator includes:
an RS flip-flop having a set input terminal receiving a first input signal and a reset input terminal receiving an inverted signal of a second input signal, and producing non-inverse and inverse outputs, wherein only when the first input signal and the inverted signal of the second input signal are both ‘true’ (i.e., the same state), the non-inverse output and the inverse output become ‘true’ as well;
a first exclusive-OR circuit receiving the first input signal and the non-inverse output; and
a second exclusive-OR circuit receiving the inverted signal of the second input signal and the inverse output.
In accordance with the second aspect of the invention, a phase comparator includes:
a first RS flip-flop having a set input terminal receiving an inverted signal of a first input signal and a reset input terminal receiving a second input signal, and producing first non-inverse and inverse outputs, wherein only when the inverted signal of the first input signal and the second input signal are both ‘true’ (i.e., the same state), the first non-inverse output and the first inverse output become ‘true’ as well;
a first exclusive-OR circuit receiving the inverted signal of the first input signal and the first non-inverse output;
a second exclusive-OR circuit receiving the second input signal and the first inverse output;
a second RS flip-flop having a set input terminal receiving a first input signal and a reset input terminal receiving the inverted signal of a second input signal, and producing second non-inverse and second inverse outputs, wherein only when the first input signal and the inverted signal of the second input signal are both ‘true’, the second non-inverse output and the second inverse output become ‘true’;
a third exclusive-OR circuit receiving the first input signal and the second non-inverse output;
a fourth exclusive-OR circuit receiving the inverted signal of the second input signal and the second inverse output;
a first OR circuit receiving an output from the first exclusive-OR circuit and an output from the third exclusive-OR circuit; and,
a second OR circuit receiving an output from the second exclusive-OR circuit and

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