Phase comparator

Details Phase comparator Phase comparator

2003-02-12

2004-10-05

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331S00100A

Reexamination Certificate

active

06801094

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a phase comparator, and more particularly to a phase comparator suitable for use in a phase locked loop (PLL) type circuit that can generate a clock signal.
BACKGROUND OF THE INVENTION
Phase comparators are widely used in phase locked loop (PLL) type circuits. PLL type circuits are commonly used to generate a clock pulse.
FIG. 4
shows a conventional phase comparator used in a PLL circuit as described in Japanese Patent Publication 2000-40957 (JP 2000-40957). Referring to
FIG. 4
, a conventional phase comparator
40
may consist of an inverter
41
, D-type flip-flops (D-F/Fs)
42
,
43
and
44
, and a selector
45
. An input signal DAT can be received by D-F/F
42
along with a clock signal CLK, that is the output of a voltage controlled oscillator (VCO). An output signal from D-F/F
42
can be latched in D-F/F
43
, which functions as a first latch, while an inverted output signal from D-F/F
42
can be latched in D-F/F
44
, which functions as a second latch.
A discriminator
46
, which is a D-F/F, can reproduce pulses of a clock signal based on input signal DAT. An output from discriminator
46
may be provided as a clock input to first latch
43
, while an inverted output from discriminator
46
may be provided as a clock input to second latch
44
. Outputs from first and second latches (
43
and
44
) are input to selector
45
. The selector
45
outputs an output value from first latch
43
when an output signal from discriminator
46
has a first level “1”, and the selector
45
outputs an output value from second latch
44
when an output signal from discriminator
46
has a second level “0.”
With the above described conventional configuration, the phase comparator
40
outputs a signal level of “1” when the phase of an input data signal DAT leads that of the clock signal CLK. Conversely, the phase comparator
40
outputs a signal level of “0” when the phase of an input data signal DAT lags that of the clock signal CLK.
FIG. 5
shows another conventional phase comparator described in “A Semidigital Dual Delay-Locked Loop,”
IEEE Journal of Solid-State Circuits
, Vol. 32, No. 11, November 1997, pp. 1683 to 1692, by Sidiropoulos et al. The phase comparator
50
of Sidiropoulos et al. includes first and second one-shot pulse generating circuits
51
and
52
, respectively, and an R-S flip-flop
53
. First and second one-shot pulse generating circuits
51
and
52
generate one-shot pulses from two input clocks C
0
and C&pgr;, respectively, to provide an inverted set input “/S” and an inverted reset input “/R.” R-S flip-flop
53
receives the inverted set input “/S” and an inverted reset input “/R,” and provides an “up” output and “dn” output. In particular, when the clock signal C&pgr; is leading in phase with respect to the clock signal C
0
, R-S flip-flop
53
provides an output signal at level “1” to output “up.” When the clock signal C&pgr; is lagging in phase with respect to the clock signal C
0
, R-S flip-flop
53
provides an output signal at level “1” to output “dn.”
In the conventional phase comparator
40
of
FIG. 4
, discriminator
46
discriminates and reproduces pulses of a clock signal CLK synchronously with respect to input data signal DAT. A comparison result is thus output after reception of the clock output from discriminator
46
. Therefore, a drawback to such an arrangement can be that a comparison result is delayed due to the output timing of discriminator
46
, hence reducing the speed at which a comparison result can be output.
In addition, in the arrangement of
FIG. 4
, a delay of inverter
41
and a set-up and hold time for D-F/F
42
can vary. Such a variation may arise from variations in a power source voltage of a phase comparator
40
, the ambient operating temperature of the phase comparator
40
, and/or process variations in the manufacturing process for the phase comparator
40
, or the like. Thus, the conventional approach of
FIG. 4
may have the drawback of variation in the phase difference that is detectable by the circuit. Such a variation results in differences in the sensitivity at which a phase comparison between the input data signal DAT and the clock signal CLK can be made. Such a detection sensitivity determines the point at which an output of a D-F/F
42
transitions between “1” and “0.”
In the conventional phase comparator
50
of
FIG. 5
, a drawback can arise when a difference in duty ratio cycles between the two input clocks C
0
and C&pgr; is large. In particular, if a duty ratio difference is sufficiently large, a phase comparison may not be accurately made.
In light of the above mentioned drawbacks of conventional phase comparators, it would be desirable to arrive at a phase comparator in which the sensitivity of a phase comparison is less susceptible, as compared to conventional approaches, to variations in power supply voltage, ambient temperature, and/or process conditions.
It would also be desirable to arrive at a phase comparator that may stably and/or rapidly provide a phase comparison result, even when the duty cycles of two input signals for comparison vary from one another.
SUMMARY OF THE INVENTION
The present invention may include a phase comparator for determining a phase lead or phase lag between phases of a first pulse signal and a second pulse signal. A phase comparator may include a reset-set (R-S) flip-flop that is set or reset in accordance with a phase difference between the first pulse signal and the second pulse signal, and a D-type flip-flop that latches an output from the R-S flip-flop according to a clock input, the clock input being a delay pulse signal obtained by delaying the second pulse signal.
According to the present invention, because a D-type flip-flop can latch an output from an R-S flip-flop according a delayed second signal, it can be possible to output a comparison result within a pulse period of the second signal. In addition, even if duty cycles of a first pulse signal and second pulse signal are not the same, a stable phase comparison between the two may be carried out.
According to one aspect of the embodiments, a first one-shot pulse generator can receive a first pulse signal as an input and provide an output to a set input of a R-S flip-flop. In addition, a second one-shot pulse generator can receive a second pulse signal as an input and provide an output to a reset input of a R-S flip-flop.
According to another aspect of the embodiments, first and second one-shot pulse generators can be composed of essentially identical circuit elements.
According to another aspect of the embodiments, a D-type flip-flop can include a logic gate that receives as inputs a delayed first signal and an output of the R-S flip-flop, and a latch circuit that latches the output of the logic gate. In particular arrangements, a logic gate can include a NAND gate. Further, a latch circuit can include at least two latch stages connected in a cascade fashion.
According to another aspect of the embodiments, a phase comparator can be composed entirely of complementary metal-insulator-semiconductor field effect transistors. In such an arrangement, a delay due to a variation in an external condition, such as a power source voltage, an ambient temperature, process conditions, or the like, are varied in the same general fashion among all such circuit elements. As a result, variations in the sensitivity of a phase comparator due to variations in such conditions can be suppressed.
The present invention may also include a phase comparator circuit having a first pulse generating circuit for generating first pulses corresponding to a first signal phase, a second pulse generating circuit for generating second pulses corresponding to a second signal phase, and a pulse receiving circuit that provides a detect output that has a first value in response to a first pulse and a second value in response to a second pulse. A phase comparator may also include an output circuit for logically combining the detect output with a delayed second signal.
According to one asp

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