Phase clocked latch having both parallel and shunt connected swi

Details Phase clocked latch having both parallel and shunt connected swi Phase clocked latch having both parallel and shunt connected swi

1993-06-15

1995-10-31

Heyman, John S.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327201, 327203, 377 79, 377105, 377117, H03K 3356

Patent

active

054633400

ABSTRACT:
A general object of the present invention is to provide a latch of which demand is small. In a half-latch 101, control signals T2 and T2C which vary at late timings are applied to a main unit for data input (update) operation while control signals T1 and T1C which vary at early timings are applied to a feedback unit for data retaining operation. The data input (update) operation is never started until the data retaining operation is completed. The data retaining operation is practiced by retaining two signals having a negative logic relation with each other in a loop made up with two inverters. A signal related to retension of data and a signal newly input never reside in the same signal line. Thus, collision of those signals is avoided, and consequently, through-current due to the collision of the signals can be reduced.

REFERENCES:
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patent: 5105100 (1992-04-01), Yamada
patent: 5202908 (1993-04-01), Hatada
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Principles of CMOS VLSI Design--A Systems Perspective. Neil H. E. Weste and Kamran Eshraghian. FIG. 5.50 (on p. 215).

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