Phase clock selector for generating a non-integer frequency...

Horology: time measuring systems or devices – Electrical time base – Solid state oscillating circuit type

Reexamination Certificate

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Details

C368S200000, C327S117000, C327S156000, C377S048000, C377S118000, C708S103000, C708S271000

Reexamination Certificate

active

06956793

ABSTRACT:
A frequency divider circuit uses a base counter to frequency divide a clock signal with period T by an integer value N and employs a cyclic rotational select circuit to select among multiple equally phase shifted signals of a multiple phase clock to generate a fractional term P/k where P is variable from 0 to k−1. The counter counts an output clock that corresponds to the output of a multiplexer selecting from among the multiple clock phases. Depending on the desired fractional term, after N counts of the output clock phases of the multiple phase clock are selected glitch free by rotationally selecting a first phase, and skipping either 0, 1, 2 . . . up to k−1 sequential phases to generate fractional terms 0, 1/k, 2/k, 3/k . . . k−1/k, respectively, thus providing frequency division corresponding to N+P/k where P may be varied from 0 to k−1.

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patent: 6845490 (2005-01-01), Natsume

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