Phase clock drive circuit and method for reduction of readout no

Details Phase clock drive circuit and method for reduction of readout no Phase clock drive circuit and method for reduction of readout no

1996-09-03

1998-11-17

Garber, Wendy

Television

Camera, system and detail

Solid-state image sensor

348241, 348317, H04N 314, H04N 5217

Patent

active

058383727

ABSTRACT:
The present invention is directed to a charge coupled device in which, during the shifting interval, the charge storage pixels are biased with an electrical potential greater than the absolute value of the CCD inversion potential and, during the charge integration interval, the charge storage pixels are biased with an electrical potential that is less than the CCD inversion potential. In this manner, the present invention substantially reduces error attributable to impact ionization or dark current.

REFERENCES:
patent: 4324988 (1982-04-01), Takemura et al.
patent: 4583003 (1986-04-01), Kimata
patent: 4651215 (1987-03-01), Bell et al.
patent: 4680636 (1987-07-01), Ooi
patent: 4716317 (1987-12-01), Spierings
patent: 4761565 (1988-08-01), Kannegundla
patent: 4954900 (1990-09-01), Frame
patent: 5237422 (1993-08-01), Kannegundla et al.
patent: 5452003 (1995-09-01), Chamberlain et al.
patent: 5483283 (1996-01-01), Kannegundla

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