Phase change memory cell with high read margin at low power...

Details Phase change memory cell with high read margin at low power... Phase change memory cell with high read margin at low power...

2008-03-25

2008-03-25

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Bulk effect device

Bulk effect switching in amorphous material

C257S003000, C257S005000, C257S529000, C257SE31029, C257SE29170, C257SE45002, C257S751000

Reexamination Certificate

active

11102350

ABSTRACT:
A memory cell device includes a first electrode, a heater adjacent the first electrode, phase-change material adjacent the heater, a second electrode adjacent the phase-change material, and isolation material adjacent the phase-change material for thermally isolating the phase-change material.

REFERENCES:
patent: 5751012 (1998-05-01), Wolstenholme et al.
patent: 5837564 (1998-11-01), Sandhu et al.
patent: 6625054 (2003-09-01), Lowrey et al.
patent: 6673648 (2004-01-01), Lowrey
patent: 6791107 (2004-09-01), Gill et al.
patent: 2002/0017701 (2002-02-01), Klersy et al.
patent: 2003/0003647 (2003-01-01), Dennison et al.
patent: 2003/0194865 (2003-10-01), Gilton
patent: 2004/0251551 (2004-12-01), Hideki
patent: 2005/0030800 (2005-02-01), Johnson et al.
patent: 2006/0092693 (2006-05-01), Chen
patent: 102 36 439 (2004-02-01), None
patent: 102 31 646 (2004-04-01), None
patent: 1 318 552 (2003-06-01), None
PCT International Search Report for International Application No. PCT/EP2006/050751 mailed on May 9, 2006 (3 pages).
H.Horii et al., “A novel cell technology using N-doped GeSbTe films for phase change RAM”, VLSI, 2003 (pp. 177-178).
Y.N. Hwang et al., “Full integration and reliability evaluation of phase-change RAM based on 0.24μm-CMOS technologies”, VLSI 2003 (pp. 173-174).
CW Jeong et al., “Switching Current Scaling and Reliability Evaluation on PRAM”, IEEE NVSMW, 2004 (pp. 28-29).
S. Lai et al., OUM-a 180 nm nonvolatile memory cell element technology for stand alone and embedded applications, IEDM 2001 (6 pgs.).
Y. H Ha, et al., “An edge contact type cell for phase change RAM featuring very low power consumption”, VLSI, 2003 (2 pgs.).
EU research project ULISSE, final report, 2003; http://www.leti.cea.fr/commun/europe/ulisse/ulisse.htm.

Affiliated with

Also associated with

Rating

Phase change memory cell with high read margin at low power... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase change memory cell with high read margin at low power..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase change memory cell with high read margin at low power... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3955388