Phase assisted synchronization detector

Details Phase assisted synchronization detector Phase assisted synchronization detector

1999-11-05

2003-12-02

Sniezek, Andrew L. (Department: 2651)

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

C360S046000

Reexamination Certificate

active

06657802

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to magnetic recording and, particularly, to an improved synchronization detector.
Sampled amplitude detectors used in magnetic recording require timing recovery in order to correctly extract the digital sequence. As shown in
FIG. 1
, data sectors
100
on magnetic disks are formatted to include an acquisition preamble
102
, a sync or synchronization mark
104
, and user data
106
. Timing recovery uses the acquisition preamble
102
to acquire the correct sampling frequency and phase before reading the user data
106
. The synchronization mark
104
demarcates the beginning of the user data.
The preamble
102
is written using the periodic non-return-to-zero (NRZ) sequence 001100110011 . . . which causes the pattern of magnetization SSNNSSNNSSNN . . . to be written on the magnetic medium. The pattern is periodic, having period
4
T, where T is the bit period. The pattern is sometimes called a
2
T pattern because the interval between successive magnetic field direction transitions is
2
T. During the read operation, the sequence of samples [x
i
, x
i+1
, . . . ], produced by the preamble is also of period
4
T. In the case of PR
4
(partial response) equalization, the sequence is ideally [1,1,−1,−1,1,1,−1,−1,1,1, . . . ,]. In the case of EPR4 (extended partial response) equalization, it is [2,0,−2,0,2,0,−2,0,2,0, . . . ]. In the general case of E
n
PR
4
, it is the convolution [1,1]
n
*[1,1,−1,−1,1,1,−1,−1,1,1, . . . ].
The preamble
102
, the sync mark
104
, and the user data
106
are read in succession. Reading the preamble
102
establishes bit synchronization. Reading the sync mark
104
establishes the absolute bit index of the first bit of the user data
106
. Once bit synchronization is established, the sync mark
104
is searched for beginning at each possible bit index (i.e., at each possible start value in the sequence) within a predetermined qualification window, the onset and time-out of which are a priori parameters. Typically, this search is done by calculating a distance metric between the ideal sequence of signal samples [s
0
, s
1
, . . . , s
L−1
] expected at the synchronization mark
104
and each block of received samples [x
i
, x
i+1
, . . . , x
i+L−1
], where the index i runs through all the bit indices in the qualification window. Typically, the first index i for which the metric does not exceed a qualification threshold is asserted to be the location of the synchronization mark
104
.
The prior art suffers from disadvantages in that a period T clock is required to clock the synchronization detector. In addition, a relatively long synchronization mark is required.
SUMMARY OF THE INVENTION
These and other drawbacks in the prior art are overcome in large part by a system and method according to the present invention. According to one implementation, a synchronization detector uses the periodicity of the preamble to limit the search for the synchronization mark. In one implementation, the search is limited to one bit phase in each block of four (4) bits. In another implementation, the search is limited to one bit phase per block of two (2) bits.
Briefly, the synchronization mark is written beginning at a known, fixed phase of the periodic preamble pattern. The signal phase estimate obtained in the course of reading the preamble is used to limit the search for the synchronization marks to the bit positions whose phase matches the estimate of the fixed, known phase.
A synchronization detector according to an embodiment of the invention includes a phase detector and a distance metric calculator. The phase detector uses the preamble readback signal to estimate the bit periods and outputs a signal indicative of this estimate. This signal is used by the distance metric calculator to limit its search for the synchronization mark to every mth bit position, where m is a predetermined integer greater than one (1).
Advantageously, the present invention allows the synchronization detector to operate on a period mT clock. Thus, the synchronization detector may use a lower speed, less expensive clock. In addition, the synchronization detector may be relatively shorter than required when m=1 to achieve a given probability of correct synchronization in the presence of noise.


REFERENCES:
patent: 4743463 (1988-05-01), Ronn et al.
patent: 4897740 (1990-01-01), Suzuki
patent: 5363360 (1994-11-01), Fairchild
patent: 5379160 (1995-01-01), Otani
patent: 5572558 (1996-11-01), Beherns
patent: 5726818 (1998-03-01), Reed et al.
patent: 5729396 (1998-03-01), Dudley et al.
patent: 5760984 (1998-06-01), Spurbeck et al.
patent: 5793548 (1998-08-01), Zook
patent: 5812334 (1998-09-01), Behrens et al.
patent: 5835295 (1998-11-01), Behrens
patent: 5892632 (1999-04-01), Behrens et al.
patent: 5909331 (1999-06-01), Behrens et al.
patent: 5909332 (1999-06-01), Spurbeck et al.
patent: 6023386 (2000-02-01), Reed et al.
patent: 6108151 (2000-08-01), Tuttle et al.
patent: 0 002 738 (1979-07-01), None
patent: WO 95/25639 (1995-09-01), None

Affiliated with

Also associated with

Rating

Phase assisted synchronization detector does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase assisted synchronization detector, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase assisted synchronization detector will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3168135