Phase and frequency detector with high resolution

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By frequency

Reexamination Certificate

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C324S076620

Reexamination Certificate

active

06194918

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to a phase detector, a method for measuring phase difference, a frequency detector and a method for measuring frequency.
GENERAL TECHNICAL BACKGROUND OF THE INVENTION
Phase detectors and frequency detectors are found in numerous applications of all modern technologies. They are widely used in areas of electronics and in different fields of communication, in particular the field of telecommunication.
Basically, a phase detector is an arrangement for measuring a phase difference between two input signals. It is well known in the art to use a start and stop counter which receives two input signals. One input signal starts the counter and the other input signal stops the counter, the counter value being representative of the phase difference between the two input signals.
In many applications there is a general need for measuring phase differences between several input signals. Should a phase detector having only two inputs be used for this purpose, it has to be duplicated several times in order to simultaneously handle a plurality of input signals.
Existing alternative techniques to measure phase differences between several input signals usually involves complicated and extensive circuitry.
In earlier phase detector arrangements supervision and maintenance are provided as additional overlay functions. The supervision is implemented as specially designed functions in separate units. This conventional solution requires a significant amount of additional circuitry.
RELATED TECHNIQUE
In U.S. Pat. No. 4,634,967 there is described a phase comparator for measuring the phase displacement between several very high stability oscillators. The phase comparator includes pairs of measuring cascades, each pair being connected to an oscillator and providing a first and second signal. Each pair has a first cascade that comprises an A/D-converter followed by a digital divider, and a second cascade that comprises a frequency changer followed by an A/D-converter. It also comprises a multiplexer, a start and stop counter and a computer making it possible to perform the phase displacement measurements.
U.S. Pat. No. 5,128,909 relates to a phase difference measuring arrangement. Phase differences between a plurality of clocks are measured based on mixing of the output signal of each clock with the output signal of a common oscillator, division of the output signal from a first one of the clocks, and detection and counting of zero up-crossings.
In U.S. Pat. No. 4,912,734 there is disclosed a high resolution event occurrence time counter operating in two clock domains, the domain of clock signal A and the domain of clock signal B. The two clock signals are generated from a common clock signal. Clock signal A is provided to a free running counter, preferably including a Johnson counter and a binary counter. The count data of the free running counter is stored in a counter register in response to clock signal B, and is stored in a second register as second time of arrival data upon the generation of a second signal, B SYNC. B SYNC, when generated, will clear a first register. The data of the counter register is stored in the first register as first time of arrival data upon the generation of a first signal, A SYNC. A SYNC, when generated, will clear the second register. The event occurrence time counter also includes a clock edge encoder which is responsive to an input signal and the clock signals A and B for generating the A SYNC and B SYNC signals. If the input signal arrives during the first half cycle of the common clock signal, then A SYNC is generated. If the input signal arrives during the second half cycle of the common clock signal, then B SYNC is generated. In this way the clock edge encoder controls which of first and second time of arrival data is to be provided as the output data of the circuit.
SUMMARY OF THE INVENTION
The present invention overcomes these and other drawbacks of the conventional arrangements.
In many applications there is a general need for measuring phase differences between several input signals.
Furthermore, there is a need for maintenance and supervision of both the phase detector and its input signals. For instance, by supervising the frequency of the input signals a malfunctioning phase detector or an erroneous input signal may be detected. In addition, it is also desirable to detect the presence of signals at the phase detector inputs.
There is a general need for a frequency detector, and, in particular, a frequency detector which uses simple circuitry and which can handle input signals of different frequencies.
In addition, regarding both phase difference measurements and frequency measurements, high resolution accuracy is desirable.
It is a first object of the present invention to provide a phase detector which is able to measure phase differences between two or more input signals by using a minimum of circuitry.
It is another object of the invention to provide a phase detector in which supervision functions are integrated in a simple manner.
Yet another object of the invention is to provide a high resolution phase detector, the resolution of which is equal to the cycle time of the clock signal that is applied to the phase detector, and preferably half the cycle time of the clock signal.
It is also an object of the invention to provide a frequency detector.
Still another object of the invention is to provide a high resolution frequency detector.
Another object of the invention is to provide means for handling measurement effecting wrap situations.
In accordance with a general inventive concept, there is provided a device responsive to a predetermined number of input signals for extracting information from the input signals.
In accordance with a first aspect of the present invention there is provided a phase detector. The phase detector is responsive to a predetermined number, K, of input signals, between which it is desired to measure phase differences.
In accordance with a first embodiment of the invention the phase detector comprises a counter, a predetermined number, K, of first registers and first subtractor means. The counter is responsive to a first clock signal for generating a counter signal. Each one of the K first registers is responsive to the counter signal and a respective one of the K input signals for updating an individual first counter value by storing the current counter value of the counter signal in response to timing information carried by the respective input signal. The first subtractor means is responsive to the first counter values for generating first difference values representing phase differences between respective pairs of the K input signals.
In general, the counter counts over more than one counter sequence, the transition between counter sequences being referred to as a wrap. In some applications of the phase detector according to the present invention, wrap situations that will effect the phase difference measurements may occur. These wrap situations are effectively handled according to a second embodiment of the invention by incorporating a correction means into the inventive phase detector. The correction means corrects for a phase difference value effecting wrap by adding a correction value to the phase difference value so as to generate a corrected phase difference value. In this way, no initialization or reset of the counter is required. The correction value may be positive as well as negative.
In accordance with a third embodiment of the present invention, the phase detector is provided with a second detection means for supervising the presence of input signals at the phase detector inputs. The second detection means detects, for each one of a set of first registers, whether the first counter value currently stored in the first register is equal to a comparison value representative of the preceding first counter value of the first register, which has been previously stored in the second detection means. If an equal to condition is detected, then a no sign

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