Phase alignment system

Details Phase alignment system Phase alignment system

2000-03-23

2002-02-26

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S241000, C327S242000

Reexamination Certificate

active

06351168

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for phase alignment generally and, more particularly, to a method and/or architecture for phase alignment of two clock signals to within a predetermined skew.
BACKGROUND OF THE INVENTION
Some conventional methods for phase alignment consist of PLLs (e.g., High-Speed Multi-Phase PLL clock buffers). The PLLs consume additional power and have an increased die size. Furthermore, conventional methods have a limited skew.
Referring to
FIG. 1
a conventional circuit
10
for phase alignment is shown. The conventional circuit
10
implements high-speed multi-phase PLL clock buffers to offer user-selectable control over system clock functions. A multiple-output clock driver provides the system integrator with functions necessary to optimize the timing of high-performance computer and communication systems.
Eighteen configurable outputs
12
a
-
12
n
each drive terminated transmission lines, while delivering minimal and specified output skews at LVTTL levels. The outputs are arranged in five banks
14
a
-
14
n
. Banks
14
a
-
14
(n−
1
) each allow a divide function of 1 to 12, while simultaneously allowing phase adjustments in 625 ps-1300 ps increments up to 10.4 ns. One of the output banks
14
a
-
14
(n−1) also includes an independent clock invert function. The feedback bank
14
n
consists of two outputs, which allows divide-by functionality from 1 to 12 and limited phase adjustments. Any one of the eighteen outputs
12
a
-
12
n
can be connected to the feedback input as well as driving other inputs.
SUMMARY OF THE INVENTION
One aspect of the present invention concerns an apparatus comprising a clock circuit and a control circuit. The clock circuit may be configured to generate a first output clock, a second output clock and a first control signal in response to (i) a first input clock, (ii) a second input clock, (iii) a second control signal and (iv) a third control signal. The control circuit may be configured to generate the second control signal and the third control signal in response to the first input clock and the first control signal. The first and second output clocks may have a skew less than a predetermined threshold.
Another aspect of the present invention concerns a circuit comprising a counter, a state machine and an update circuit, The counter may be configured to present a first control signal and a second control signal in response to a reset signal and a third control signal. The state machine may be configured to generate a select signal in response to (i) the reset signal, (ii) the first control signal and (iii) the second control signal. The update circuit may be configured to generate a fourth control signal in response to the select signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for phase alignment of two signals that may provide (i) a simplistic and purely digital logic design to align the two signals within a predetermined skew, (ii) the ability to shift a phase of a reference clock using metal fuses and/or programmable registers that may allow change of (a) data setup and/or (b) hold time in high speed communication systems, (iii) a digital phase alignment system and/or (iv) an updatable configuration method.


REFERENCES:
patent: 4504862 (1985-03-01), Achstaetter
patent: 4908582 (1990-03-01), Kawano et al.
patent: 5049766 (1991-09-01), Van Driest et al.
patent: 5825226 (1998-10-01), Ferraiolo et al.
patent: 5875219 (1999-02-01), Kim
patent: 6054887 (2000-04-01), Horie et al.
RoboClock II™ CY7B994V/CY7B993V, High-Speed Multi-Phase PLL Clock Buffer, Cypress Semiconductor Corporation, Jun. 13, 2000, pp. 1-14.

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