Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Converging with plural inputs and single output
Patent
1997-12-23
2000-08-15
Nuton, My-Trang
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Converging with plural inputs and single output
327284, H03K 1762, H03H 1126
Patent
active
061042285
ABSTRACT:
A system for aligning the phase of signals generated by a selectable standby clock source which has a predetermined frequency with the phase of signals generated by a selected clock source which has the same frequency as signals generated by the standby clock source. The system comprises (1) a delay line having a plurality of delay elements which is configured to receive the signals generated by the standby clock source so that the output signal of each delay element is a delayed version of the standby clock source; (2) a decoder configured to receive each of the delayed versions of the signals generated by the standby clock signal source and generates a selection signal corresponding to a desired one of the delayed version signals that is aligned with signals generated by the selected clock source within a specifiable phase difference; and (3) a selector configured to receive the selection signal so as to select the desired delayed version signal as a new standby clock source.
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patent: 5708382 (1998-01-01), Park
patent: 5818890 (1998-10-01), Ford et al.
Jeff Sontag, Robert Leonowich, A Monolithic CMOS 10 MHz DPLL for Burst-Mode Data Retiming, 1990 IEEE International Solid State Circuit Conference, 2/16 v.33.
Lucent Technologies - Inc.
Nuton My-Trang
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