Phase adjustment system

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

328 55, 328104, 328154, 307269, 331 2, 331 47, 331 49, H03K 526

Patent

active

046511032

ABSTRACT:
Synchronization facilities are disclosed for maintaining error free timing of a digital system when control of the system timing is switched between a plurality of clock sources. The signal of each source is applied to an associated counter divider whose output is applied to switch facilities which extend the output of only one divider at a time as a reference clock source to the digital system. The dividers for the other sources are forcibly reset each time the divider of the reference source advances from its all 1s to its reset (all 0s) position. This maintains the output signals of all dividers in phase with each other to prevent disturbances to the digital system when its timing is switched between clock sources.

REFERENCES:
patent: 3737674 (1973-06-01), Butler
patent: 4185245 (1980-01-01), Fellinger et al.
patent: 4229699 (1980-10-01), Frissell
patent: 4419629 (1983-12-01), O'Brien
patent: 4560939 (1985-12-01), De Karske et al.

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