Phase adjustment method and circuit for DLL-based serial...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S158000

Reexamination Certificate

active

07321248

ABSTRACT:
A delay locked loop circuit with a first flip flop driven by a 0° clock and receiving the input data. A second flip flop by a 180° clock and receiving the input data. A first demultiplexer receives an output of the first flip flop and outputs peak data. A second demultiplexer receives an output of the second flip flop and outputs zero data. A timing recovery circuit outputs phase control bits based on the zero data and the peak data. A first phase interpolator outputs the 0° clock based on the phase control signal. A second phase interpolator outputs the 180° clock based on the phase control signal. A phase register receives the phase control signal from the timing recovery circuit. The first and second flip flops can be D flip flops. The first and second phase interpolators adjust relative phases of the 0° clock and 180° clock based on the phase control signal. The phase control signal can be a digital signal comprising a plurality of bits corresponding to a phase relationship between the 0° clock and 180° clock. The timing recovery circuit can be a digital circuit. The phase control signal is used to maintain a transition of the 0° clock near a center of an “eye” in the input data.

REFERENCES:
patent: 2004/0161070 (2004-08-01), Yin et al.
patent: 2004/0252804 (2004-12-01), Aoyama

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