Pulse or digital communications – Miscellaneous
Reexamination Certificate
2000-07-17
2004-03-09
Corrielus, Jean B. (Department: 2631)
Pulse or digital communications
Miscellaneous
C327S291000, C327S002000
Reexamination Certificate
active
06704384
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a phase adjusting circuit and a semiconductor memory incorporating the same, and more specifically to a phase adjusting circuit for adjusting the phase of a clock signal to the phase of a read/write data signal, and a semiconductor memory internally comprising the same.
In a semiconductor memory configured to transfer a read/write data in a time division manner, data is received and transmitted in synchronism with a clock signal. In this type of semiconductor memory, since the read/write data is transferred in the time division manner, the number of signal lines has been remarkably reduced.
When the clock signal is used, a clock skew becomes a problem. In order to reduce the clock skew, it becomes necessary to adjust the phase of the clock signal supplied to an internal circuit. Under this circumstance, it is an ordinary practice to provide a phase adjusting circuit in the semiconductor memory.
For example, in a Rambus DRAM, an internal clock signal supplied to data output circuits is phase-adjusted so as to phase-match a plurality of data output signals to one another. In the Rambus DRAM, furthermore, the internal clock signal supplied to the data output circuits is phase-adjusted to synchronize an outputting timing of an output data with a predetermined active edge of an external clock signal in order to apparently realize a high speed access.
In order to adjust the phase of the internal clock signal as mentioned above, it is sufficient if a phase adjusting circuit compares the phase of the external clock signal supplied from an external circuit with the phase of a dummy output signal. This dummy output signal is generated by a dummy output circuit which receives and delays the internal clock signal by the same time as a delay time from the moment the output circuit receives the internal clock signal to the moment the output circuit actually outputs the data signal. The phase of the external clock signal is compared with the phase of the dummy output signal, and the internal clock is generated to make the phase of the external clock signal coincident with the phase of the dummy output signal, so that the phase of the external clock signal will be coincident with the phase of the data output signal.
The condition for generating the internal clock signal as mentioned above, is expressed by a digital code, which is then converted into an analog value. The internal clock is delayed by the required amount corresponding to the analog value, and the delayed internal clock is supplied to the data output circuits, so that the phase of the external clock signal is matched with the phase of the data output signal.
However, at the time of adjusting the phase of the internal clock signal, many signals of the digital code changes at one time, so that a noise occurs. Because of this noise, the timing of the internal clock signal is temporarily greatly deviated in some cases. As a result, there occurs possibility that not only the internal clock signal having a desired phase cannot be obtained, but also the duty ratio of the internal clock is deteriorated, so that necessary setup time and hold time cannot be ensured in a circuit supplied with the internal clock signal, with the result that an expected operation is not carried out and a malfunction occurs.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a phase adjusting circuit which has overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a phase adjusting circuit capable of stably adjusting the phase without being influenced by noises occurring in the phase adjustment.
The above and other objects of the present invention are achieved in accordance with the present invention by a phase adjusting circuit comprising a differential amplifier receiving an external input signal and having a controllable current source, a delay means for delaying an output signal of the differential amplifier by a predetermined length of time, a comparator for phase-comparing the external input signal with the output signal delayed by the delay means, a digital code generating circuit receiving a comparison result from the comparator for generating a digital code composed of a plurality of bits, and a D/A converter receiving the digital code for generating a control signal to the controllable current source, wherein the D/A converter outputs a first control signal corresponding to a first digital code outputted from the digital code generating circuit, and when the first digital code changes to a second digital code, the D/A converter maintains the first control signal for a predetermined period of time, and then, outputs a second control signal corresponding to the second digital code after the predetermined period of time has elapsed.
According to another aspect of the present invention, there is provided a semiconductor memory comprising a memory cell array, a phase adjusting circuit receiving an external clock signal to generate an internal clock signal and having the function for adjusting the phase of the internal clock signal, a data outputting circuit for outputting data from the memory cell array in response to the internal clock signal, the phase adjusting circuit including a differential amplifier receiving the external clock signal to output the internal clock signal and having a controllable current source, a delay means for delaying the internal clock signal outputted from the differential amplifier by a delay time of the data outputting circuit, a comparator for phase-comparing the external clock signal with the internal clock signal delayed by the delay means, a digital code generating circuit receiving a comparison result from the comparator for generating a digital code composed of a plurality of bits, and a D/A converter receiving the digital code for generating a control signal controlling the controllable current source of the differential amplifier, wherein the D/A converter outputs a first control signal corresponding to a first digital code outputted from digital code generating circuit, and when the first digital code changes to a second digital code, the D/A converter maintains the first control signal for a predetermined period of time, and then, outputs a second control signal corresponding to the second digital code after the predetermined period of time has elapsed.
REFERENCES:
patent: 6265903 (2001-07-01), Takahashi
patent: 6417715 (2002-07-01), Hamamoto et al.
patent: 2001/0052808 (2001-12-01), Hamamoto et al.
patent: 2002/0053933 (2002-05-01), Takahashi
patent: 2002/0057122 (2002-05-01), Takahashi
Corrielus Jean B.
McGinn & Gibb PLLC
NEC Corporation
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