Phase adjusting circuit

Details Phase adjusting circuit Phase adjusting circuit

1989-07-18

1991-10-08

Chin, Stephen

Pulse or digital communications

Spread spectrum

Direct sequence

307510, 328 72, H04L 700

Patent

active

050561200

ABSTRACT:
A phase adjusting circuit for adjusting a phase of each bit of serial data by synchronizing with a system clock. The phase adjusting circuit includes a plurality of registers. Each bit of data is input into a corresponding one of the plurality of registers in a predetermined cyclic order, synchronized with a receiving clock which is extracted from the data, and outputting outputs of the registers in parallel. The outputs are each selected in a selector circuit under a control of the selector control signal in the same order as the above input to the registers. The selector control signal is generated by detecting a phase relationship between phases of the receiving clock and the system clock, and generating a selector control signal having a phase which is determined according to the phase relationship. Then, each bit of the above selected output is synchronized with the system clock.

REFERENCES:
patent: 3959589 (1976-05-01), von Roesgen
patent: 4010323 (1977-03-01), Peck
patent: 4017803 (1977-04-01), Baker
patent: 4119796 (1978-10-01), Jones
patent: 4520408 (1985-05-01), Velasquez
patent: 4672639 (1987-06-01), Tanabe et al.
patent: 4756011 (1988-07-01), Cordell
patent: 4805198 (1989-02-01), Stern et al.
patent: 4841551 (1989-06-01), Avaneas

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