Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-01-27
2002-03-26
Nguyen, Chau (Department: 2663)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C711S149000, C370S465000
Reexamination Certificate
active
06363076
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to bus interfaces and more particularly to bus interfaces for interfacing between buses of different speeds.
BACKGROUND OF THE INVENTION
In recent years, more and more emphasis has been placed on networking computers to provide local area networks. In such a computer network, one critical component is the network interface which allows communication between a users computer and other computers in the network such as a server or other computer workstation. Typically, a computer's network interface, among other things, allows communications between the high speed internal bus of the computer and the lower speed external bus of the network.
One example of communication between a high speed bus and a lower speed bus occurs in such network interface cards (NIC) such as an Ethernet adapter. In a typical Ethernet adapter for use in a typical personal computer, the adapter interfaces with the processor and other hardware of the personal computer through a Peripheral Component Interconnect bus (PCI bus) internal to the computer. The PCI bus is a synchronous bus which operates on 30 nanosecond cycles. The Ethernet adapter also communicates with the Ethernet media which operates at a different speed from the PCI bus. In order to accommodate the differing operating speeds of the buses with which the adapter communicates, a buffering scheme may be employed by the adapter where data from either bus is first stored in the adapter before being transmitted onto the other bus.
In making the conversion from the PCI bus to the Ethernet media, the communication typically passes through differing clock domains. For example, in a 10/100 Ethernet adapter the data may be received from the 30 ns/cycle synchronous PCI bus and may be stored in transmit and receive buffers which are accessed by a 40 ns/cycle synchronous internal adapter bus. This transfer of data across clock domains may present problems in the design of a network adapter.
One technique to overcome the differences between the higher speed PCI bus and a lower speed internal bus of an Ethernet adapter is to store the data received from the PCI bus in a buffer and then transmit the data to the transmit buffer or receive data from the receive buffer and transmit the data onto the PCI bus. While this buffering technique allows for communication across the two clock domains of the two buses, such a buffering technique typically requires a buffer that is large enough to hold all of the data of a block of data transmitted on the PCI bus. Such a large buffer may be impractical or expensive to implement. Furthermore, the speed with which information could be transferred between the PCI bus and the internal transmit and receive buffers may be reduced by the delay of the buffering operation.
Another example of an interface between two differing buses is illustrated in U.S. Pat. No. 4,400,772 which describes the use of a random access memory (RAM) buffer and the isolation of the buses with a bus buffer. This dual use method, however, is limited to blocks of data which are no larger than the size of the RAM buffer. Furthermore, the operations of the interface are serial in that when one operation is loading RAM the other user of the RAM is isolated from the bus. Data is first loaded into the RAM and then, after the load operation is completed, read from the RAM, thus creating a latency delay between the transmission and receipt of the data.
Other examples of the use of buffers, RAMs and first-in-first-out buffers are seen in U.S. Pat. Nos. 5,627,568, 5,623,608, 5,471,581, 5,485,684, 5,428,649, 5,210,749, 4,884,286, 4,849,970, and 4,629,894.
In light of the above discussion, a need exists for improvement in the interfacing between buses operating at different speeds which would allow devices operating at different speeds to more efficiently communicate.
SUMMARY OF THE INVENTION
In view of the above discussion, it is an object of the present invention to provide increased performance in interfacing between buses operating at different speeds.
A further object of the present invention is to provide for decreased latency in transferring data between differing clock domains.
Still another object of the present invention is to provide for decreased size interface circuits for interfacing between differing clock domains.
These and other objects of the present invention are provided by methods, systems or apparatus. and computer program products that interface between two data buses operating at different speeds. Such interfaces utilize a buffer which has an apparent size larger than the physical size of the buffer to receive blocks of data which are larger than the size of the buffer. The apparent size of the buffer is created by simultaneously writing data to and reading data from the buffer such that the same storage locations may be used more than once to hold the data. The present invention may be utilized for receiving data from either a high speed for transmission to a lower speed bus or the lower speed bus for transmission to the higher speed bus.
In one embodiment of the present invention the interface between buses of differing speeds involves receiving a block of data at a first port of a dual port buffer from a first data bus at a first speed. However, the amount of data in the block of data is larger than the amount of data which may be simultaneously stored in the dual port buffer. A first portion of the data from the block of data is transmitted from a second port of the dual port buffer to the second data bus at a second speed, slower than the first speed, while a remaining portion of the data from the block of data is received by the dual port buffer.
Preferably, the amount of data in the block of data is less than or equal to the amount of data which may be simultaneously stored in the dual port buffer multiplied by the ratio of the rate at which data may be received by the dual port buffer from the first data bus to the difference between the rate at which data may be received by the dual port buffer from the first data bus and the rate at which data may be transmitted on the second data bus by the dual port buffer.
By simultaneously storing and transmitting data from the dual port buffer, the present invention allows for use of a dual port buffer which is smaller than the block of data. Thus, the size of the buffer may be reduced over conventional interfaces. Alternatively, for a given size buffer, the amount of data in a block of data may be increased, thus increasing the efficiency of data transfers as the amount of data per transfer may be increased without increasing the overhead for a transfer. Furthermore, because the transfer of data into and out of the buffer occurs at the same time the latency through the buffer may be reduced.
In particular embodiments of the present invention, initial data from the block of data is stored in the dual port buffer. The amount of this initial data from the block of data corresponds to the amount of data which may be simultaneously stored in the dual port buffer. Additional data from the block of data is then stored in the dual port buffer so as to overwrite at least a portion of the initial data. Preferably, the additional amount of data is stored in a same sequence of storage locations of the dual port buffer beginning with the first storage location of the initial data from the block of data so as to overwrite at least a portion of the initial data.
In a further embodiment of the present invention, a first portion of a block of data at a second port of a dual port buffer is received from a second data bus operating at a second speed. Again, the amount of data in the block of data is larger than an amount of data which may be simultaneously stored in the dual port buffer and the first portion of the block of data comprises an amount less than or equal to the amount of data which may be simultaneously stored in the dual port buffer. The first portion of the data from the block of data is transmitted from a first port of the dual po
Allison Samuel Steven
Barker Kenneth James
Lee Joseph Kinman
International Business Machines - Corporation
Lee Andy
Myers Bigel Sibley & Sajovec P.A.
Nguyen Chau
LandOfFree
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