Pulse or digital communications – Transmitters – Angle modulation
Reexamination Certificate
1998-04-17
2002-05-28
Corrielus, Jean (Department: 2631)
Pulse or digital communications
Transmitters
Angle modulation
C332S103000, C708S307000
Reexamination Certificate
active
06396880
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to the field of digital communications, and in particular to a &pgr;/4 differential quadrature phase shift keying (DQPSK) encoder that employs a rotated and offset signalling constellation, and to a reduced complexity &pgr;/4 DQPSK modulator.
Due to the widespread popularity of the World Wide Web, Internet traffic is at an all time high and rapidly increasing. The resulting congestion is taking its toll on users and telephone companies alike. Users are often frustrated by the length of time it takes to download complex graphics and videos. For example, a ten megabyte video clip which is the equivalent of a four minute movie, takes approximately ninety-three minutes using a 14.4 kilobyte modem and forty-six minutes using a 28.8 kilobyte modem. In addition, lengthy data transmissions are tying up telephone company switches that were designed to handle brief telephone calls.
As an alternative to data communications over telephone lines, cable modems have emerged as a technology which dramatically increases the amount of data that can be transferred over the Internet. Cable modems are used primarily for home Internet access since they use the existing cable television wiring, and most homes are wired for cable (in contrast to businesses).
There are two primary classes of cable modems. The first are two-way devices which allow a user to both upload and download information over the coax cable. The two-way devices are also referred to as hybrid fiber-coax (HFC) modems. The second class of cable modems are one-way devices which only allow a user to download information over the cable. A user must employ a conventional telephone dial-up connection to issue commands.
FIG. 1
illustrates a functional block diagram of a system
10
which employs HFC modems. The system
10
includes a plurality of user sites
12
,
14
which each include a cable modem
16
,
18
and a computer
20
,
22
, respectively. The user site
12
may also connect a TV
24
to the cable modem
16
to receive TV signals. The modems
16
,
18
communicate with a neighborhood concentrator
26
over conventional coax cable lines
28
,
30
. To complete the connection to the Internet, the neighborhood concentrator
26
communicates over a fiber-optic network
32
with a cable provider's main facility
34
, which establishes the high speed connection to the Internet. A number of signal encoding techniques are used to transmit the data over the cable lines. These techniques include BPSK, QPSK, &pgr;/4 DQPSK and QAM.
A problem with existing &pgr;/4 DQPSK modulators is the size of the integrated circuit which contains the modulator and the power drawn by the circuit. One source of the problem is the internal bus width required to accurately represent the eight(8) constellation points used for &pgr;/4 DQPSK signalling.
FIG. 2
illustrates a plot of a signalling constellation
40
for a conventional &pgr;/4 DQPSK modulator. The constellation includes eight constellation points
42
-
49
, and each point is uniquely defined in two-dimensions (I, Q).
One of the numbers which must be represented in the constellation
40
is the value
1
/SRQT(
2
). To represent this value using a binary number, at least ten bits are generally required to ensure the quantization error is relatively insignificant. Therefore, following the encoding step, the subsequent processing steps of the &pgr;/4 DQPSK modulator such as digital filtering, and the multiplications and additions associated therewith must be configured to work with at least ten bits. This quickly leads to a large number of registers, flip-flops and other sequential and combinational logic devices within the circuit which necessitates an increase in the chip size and the amount of power used by the circuit.
This problem is not limited to &pgr;/4 DQPSK modulators used for HFC modems. &pgr;/4 DQPSK modulators are used in a wide variety of communication applications including wireless cellular, including system employing the IS-54 standard, and each of these applications is subject to the need for a large number of sequential and combination logic devices. This is particularly troublesome in applications such as handheld transceivers where it is desirable to reduce the modulator size and power consumption.
Therefore, there is a need for a reduced complexity &pgr;/4 DQPSK modulator.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a &pgr;/4 DQPSK modulator of reduced complexity.
A further object is to provide a &pgr;/4 DQPSK encoder.
Briefly, according to the present invention, a &pgr;/4 DQPSK modulator includes a rotated and offset &pgr;/4 encoder that provides encoded I, Q constellation indices values using positive integers. The positive integer I and Q values are input to a digital filter that provides filtered I, Q constellation indices values. These filtered values are then rotated and offset back to conventional &pgr;/4 DQPSK constellation values, modulated and transmitted.
Since the rotated and offset &pgr;/4 encoder provides I, Q constellation indices as positive integers, the filters are implemented as multiplierless digital filters which significantly reduces the complexity of the filters. Specifically, the multiplierless digital filters can be implemented using shift registers and summers. In a preferred embodiment the filters are programmable. In addition, using positive integers to represent the rotated and offset &pgr;/4 signalling constellation indices allows the indices to be represented as a binary value with less bits in contrast to prior art systems. Significantly, representing the indices with less bits further reduces the complexity of the digital filters.
Advantageously, encoding the &pgr;/4 DQPSK signalling constellation indices with positive integers reduces the number to bits required to represent the indices, and allows the use of multiplierless digital filters, which together reduce the size of the integrated circuit for the modulator and the power drawn by the circuit.
These and other objects, features and advantages of the present invention will become apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings.
REFERENCES:
patent: 5140613 (1992-08-01), Birgenheier et al.
patent: 5222103 (1993-06-01), Gross
patent: 5260673 (1993-11-01), Pham
patent: 5379322 (1995-01-01), Kosaka et al.
patent: 5379323 (1995-01-01), Nakaya
patent: 5438592 (1995-08-01), Boccuzzi
patent: 5526381 (1996-06-01), Boccuzzi
patent: 5528631 (1996-06-01), Hayashi et al.
patent: 5546428 (1996-08-01), Nam et al.
patent: 5604770 (1997-02-01), Fetz
patent: 5822363 (1998-10-01), Le Roy
Kobayashi et al., IEEE Custom Integrated Circuits Conference, “An Integrated &pgr;/4-Shift QPSK Baseband Modulator”, 1994.
Andrew D. Booth,A Signed Binary Muliplication Technique, Oxford University Press, 1951.
Henry Samueli,The Design of Muliplierless Digital Data Transmission Filters with Powers-of-tow-Coefficients, 1990.
Les Freed, Net Tools, PC Magazine, Feb. 10, 1998.
Corrielus Jean
Samuels , Gauthier & Stevens, LLP
LandOfFree
&pgr;/4 DQPSK encoder and modulator does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with &pgr;/4 DQPSK encoder and modulator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and &pgr;/4 DQPSK encoder and modulator will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2899536