Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2008-06-03
2008-06-03
Nguyen, Matthew V. (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S282000, C361S018000
Reexamination Certificate
active
07382114
ABSTRACT:
To prevent a voltage glitch in the regulated DC output voltage of a PWM/PFM DC-DC converter when switching between PFM and PMW modes, the error amplifier of the converter's PWM regulation path is provided with a DC voltage offset correction mechanism. This mechanism “zeros-out” DC voltage offsets that may be present in the voltage regulation path, thereby enabling the error amplifier to accurately regulate the converter's output voltage. When the converter transitions between PFM and PWM modes, the DC offset correction mechanism establishes initial conditions of the error amplifier that effectively ensure that the converter's regulated output voltage at the beginning of a new “switched-to” PWM mode cycle is DC offset-free.
REFERENCES:
patent: 5548206 (1996-08-01), Soo
patent: 6314007 (2001-11-01), Johnson et al.
patent: 6914418 (2005-07-01), Sung
patent: 7088599 (2006-08-01), Muska et al.
patent: 2007/0085519 (2007-04-01), Xu
Fogg & Powers LLC
Intersil America's Inc.
Nguyen Matthew V.
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