pFET nonvolatile memory

Details pFET nonvolatile memory pFET nonvolatile memory

2007-05-22

2007-05-22

Lam, David (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185140, C365S185280

Reexamination Certificate

active

10839985

ABSTRACT:
A nonvolatile memory cell is constructed using a floating-gate (FG) pFET Readout Transistor (RT) having its source tied to a power source (Vdd) and its drain providing a current which can be sensed to determine a cell state. The gate of the RT provides for charge/information storage. A control capacitor structure (CCS) having terminals coupled to a first voltage source and the FG and a tunneling capacitor structure (TCS) having terminals coupled to a second voltage source and the FG are utilized in each embodiment. The CCS has much more capacitance than the TCS. Manipulation of the voltages applied to the first voltage source and second voltage source (and Vdd) controls an electric field across the CCS and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons onto and off of the FG, thus controlling the charge on the FG and the information stored thereon.

REFERENCES:
patent: 4935702 (1990-06-01), Mead et al.
patent: 5068622 (1991-11-01), Mead et al.
patent: 5272368 (1993-12-01), Turner et al.
patent: 5430670 (1995-07-01), Rosenthal
patent: 5438542 (1995-08-01), Atsumi et al.
patent: 5463348 (1995-10-01), Sarpeshkar et al.
patent: 5517044 (1996-05-01), Koyama
patent: 5541878 (1996-07-01), LeMoncheck et al.
patent: 5596524 (1997-01-01), Lin et al.
patent: 5617358 (1997-04-01), Kodama
patent: 5627392 (1997-05-01), Diorio et al.
patent: 5633518 (1997-05-01), Broze
patent: 5666307 (1997-09-01), Chang
patent: 5687118 (1997-11-01), Chang
patent: 5691939 (1997-11-01), Chang et al.
patent: 5706227 (1998-01-01), Chang et al.
patent: 5717636 (1998-02-01), Dallabora et al.
patent: 5736764 (1998-04-01), Chang
patent: 5761121 (1998-06-01), Chang
patent: 5777361 (1998-07-01), Parris et al.
patent: 5790060 (1998-08-01), Tesch
patent: 5796656 (1998-08-01), Kowshik et al.
patent: 5798967 (1998-08-01), Sarin et al.
patent: 5801994 (1998-09-01), Chang et al.
patent: 5825063 (1998-10-01), Diorio et al.
patent: 5841165 (1998-11-01), Chang et al.
patent: 5844300 (1998-12-01), Alavi et al.
patent: 5886566 (1999-03-01), Park et al.
patent: 5898613 (1999-04-01), Diorio et al.
patent: 5901084 (1999-05-01), Ohnakado
patent: 5912842 (1999-06-01), Chang et al.
patent: 5939945 (1999-08-01), Thewes et al.
patent: 5966329 (1999-10-01), Hsu et al.
patent: 5969987 (1999-10-01), Blyth et al.
patent: 5972804 (1999-10-01), Tobin et al.
patent: 5982669 (1999-11-01), Kalnitsky
patent: 5990512 (1999-11-01), Diorio et al.
patent: 6028789 (2000-02-01), Mehta et al.
patent: 6055185 (2000-04-01), Kalnitsky et al.
patent: 6081451 (2000-06-01), Kalnitsky et al.
patent: 6125053 (2000-09-01), Diorio et al.
patent: 6137722 (2000-10-01), Kalnitsky et al.
patent: 6137723 (2000-10-01), Bergemont et al.
patent: 6137724 (2000-10-01), Kalnitsky et al.
patent: 6144581 (2000-11-01), Diorio et al.
patent: 6166954 (2000-12-01), Chern
patent: 6166978 (2000-12-01), Goto
patent: 6190968 (2001-02-01), Kalnitsky et al.
patent: 6208557 (2001-03-01), Bergemont et al.
patent: 6294427 (2001-09-01), Furuhata et al.
patent: 6320788 (2001-11-01), Sansbury et al.
patent: 6452835 (2002-09-01), Diorio et al.
patent: 6469937 (2002-10-01), Fuchigami et al.
patent: 6479863 (2002-11-01), Caywood
patent: 6534816 (2003-03-01), Caywood
patent: 6563731 (2003-05-01), Bergemont
patent: 6611463 (2003-08-01), Mehta et al.
patent: 6646919 (2003-11-01), Madurawe et al.
patent: 6678190 (2004-01-01), Yang et al.
patent: 6853583 (2005-02-01), Diorio et al.
patent: 2002/0008271 (2002-01-01), Hsu et al.
patent: 2003/0206437 (2003-11-01), Diorio et al.
patent: 2004/0004861 (2004-01-01), Srinivas et al.
patent: 2004/0021166 (2004-02-01), Hyde et al.
patent: 2004/0037127 (2004-02-01), Lindhorst et al.
patent: 2004/0052113 (2004-03-01), Diorio et al.
patent: 2004/0195593 (2004-10-01), Diorio et al.
patent: 0 298 618 (1989-01-01), None
patent: 0 776 049 (1997-05-01), None
patent: 0 778 623 (2001-07-01), None
Carley, “Trimming Analog Circuits Using Floating-Gate Analog MOS Memory”, IEEE Journal of Solid-State Circuits, vol. 24, No. 6, Dec. 1989.
Chung , et al., “N-Channel Versus P-Channel Flash EEPROM-Which One Has Better Reliabilities”, IEEE Annual International Reliability, 2001, pp. 67-72.
Diorio, et al., “A Floating-Gate MOS Learning Array with Locally Computed Weight Updates”, IEEE Transactions on Electron Devices, vol. 44, No. 12, Dec. 1997, pp. 1-10.
Diorio, et al., “A High-Resolution Non-Volatile Analog Memory Cell”, IEEE Intl. Symp. on Circuits and Systems, vol. 3, 1995, pp. 2233-2236.
Herdt, et al., “Analysis, Measurement, and Simulation of Dynamic Write Inhibit in an nvSRAM Cell”, IEEE Transactions on Electron Devices, vol. 39, No. 5, May 1992, pp. 1191-1196.
Vittoz, et al., “Dynamic Analog Techniques”, Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, Chapter 4, Second Edition, 1994, pp. 97-124.
Ying Shi, et al., “Polarity Dependent Gate Tunneling Currents in Dual-Gate CMOSFET's”, IEEE Transactions on Electron Devices, vol. 45, No. 11, Nov. 1998, pp. 2355-2360.
Partial International Search for International Application No. PCT/US03/31792, date mailed Apr. 2, 2004.
Chang, et al., “A CMOS-Compatible Single-Poly Cell for Use as Non- Volatile Memory”, International Semiconductor Device Date Research Symposium, Dec. 1-3, 1999, pp. 50-57.
Chang, et al., “Non-Volatile Memory Device with True CMOS Compatibility”, Electronics Letters, vol. 35, No. 17, Aug. 19, 1999, pp. 1443-1445.
Diorio, “A p-Channel MOS Synapse Transistor with Self-Convergent Memory Writes”, IEEE Transaction On Electron Devices, vol. 47, No. 2, pp. 464-472, Feb. 2000.
Usuki, Tatsuya, et al., “Direct Tunneling Memory: Trade-off Between Nonvolatility and High-Endurance with Low Voltage Operations”, Nonvolatile Semiconductor Workshop Symposium, Aug. 12, 2001; pp. 80-81.
Jaroslav Raszka et al., “Embedded Flash Memory for Security Applications in a 0.13 um CMOS Logic Process”, IEEE International Solid-State Circuits Conference, 2004, pp. 46-47.
Invitation to Pay Additional Fees, for application PCT/US2005/015606, mailed Nov. 18, 2005.
The International Search Report for International application No. PCT/US2005/015606, date of mailing Feb. 24, 2006.

Affiliated with

Also associated with

Rating

pFET nonvolatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with pFET nonvolatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and pFET nonvolatile memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3741353