Personalization structure for semiconductor devices

Details Personalization structure for semiconductor devices Personalization structure for semiconductor devices

1996-07-25

1999-03-16

Whitehead, Jr., Carl W.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257734, 257737, 257779, 257780, H01L 2348, H01L 2352

Patent

active

058834354

ABSTRACT:
The preferred embodiment of the present invention provides a structure and method for personalizing a semiconductor device in the context of a bump array connection to packaging, substrates and such. The preferred embodiment method uses a plurality of conduction lines on said semiconductor device, including a plurality of landing lines and personalization lines. Vias are opened to the plurality of landing lines and selectively opened to a portion of the personalization lines. Connections are made between the opened personalization lines with bumps deposited as part of the bump array.

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patent: 5436412 (1995-07-01), Ahmad et al.
patent: 5438166 (1995-08-01), Carey et al.
Bartlett, C., "Multichip Packaging Design for VLSI-Based Systems", IEEE Transactions on Components, Hybrids and Manufacturing Technology, vol. CHMT-12, No. 4, Dec. 1987, pp. 647-653.
Cronin, J.E., "Method for Elimination of Scratches in Polished Damascene Conductors", Research Disclosure, Feb. 1991, Number 322, Kenneth Maso Publications, Ltd. England.
Heinen, et al., "Multichip Assembly with Flipped Integrated Circuits", IEEE Transactions on Components, Hybrids and Manufacturing Technology, vol. 12, No. 4, Dec. 1989, pp. 650-657.
Miller, "Controlled Collapse Reflow Chip Joining", IBM Res. Develop., pp. 239-250.

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