Personalizable masterslice substrate for semiconductor chips

Details Personalizable masterslice substrate for semiconductor chips Personalizable masterslice substrate for semiconductor chips

1984-02-15

1986-07-22

Edlow, Martin H.

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

357 68, 357 74, 361414, H01L 3904, H01L 2302, H01L 2308

Patent

active

046022716

ABSTRACT:
A substrate for packaging semiconductor chips is provided which is structured with conductors having opposite ends terminating in a mounting surface and intermediate portions extending beneath the surface. The ends of the conductors are arranged in repeating patterns longitudinally along the substrate separated by orthogonal strips free of conductor ends to allow for dense surface wiring. The repeating patterns are arranged to allow for chip mounting sites having sufficient spacing to allow for surface wiring. In this way chips in the same and repeat pattern can be connected by personalized surface wiring and preset substrate conductors.

REFERENCES:
patent: 4193082 (1980-03-01), Dougherty
patent: 4202007 (1980-05-01), Dougherty et al.
patent: 4220917 (1980-09-01), McMahon, Jr.
patent: 4322778 (1982-03-01), Barbour et al.
Johnson et al., IBM Tech. Dis. Bulletin, vol. 22, #5, Oct. 1979, pp. 1841-1842, "Multilayer Ceramic Fixed Layer Substrate Design".

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