Personal computer with processor reset control

Details Personal computer with processor reset control Personal computer with processor reset control

1994-06-20

1997-05-13

Auve, Glenn A.

395308, 395293, G06F 1314

Patent

active

056300786

ABSTRACT:
This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.

REFERENCES:
patent: 4768162 (1988-08-01), Nishimura
patent: 4787032 (1988-11-01), Culley
patent: 4788661 (1988-11-01), Morita
patent: 5007014 (1991-04-01), Nishimura
patent: 5125088 (1992-06-01), Culley
patent: 5148380 (1992-09-01), Lin et al.
patent: 5170481 (1992-12-01), Begun et al.

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