Personal computer memory bank parity error indicator

Details Personal computer memory bank parity error indicator Personal computer memory bank parity error indicator

1992-02-07

1993-01-05

Beausoliel, Robert W.

Excavating

371 216, G06F 1110

Patent

active

051777479

ABSTRACT:
A personal computer has two memory banks respectively connected to two parity check units operative to detect parity errors. Upon doing so, each unit feeds a parity error signal to a separate latch. The latches are connected to a logic circuit which is in turn connected to an interrupt controller that initiates an interrupt when a parity error occurs. One latch is further connected to a check bit of a register of an I/O port and the check bit is set by the one latch. An interrupt handler reads the register and provides messages indicating which memory bank caused the parity error.

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