Personal computer having memory system with write-through cache

Details Personal computer having memory system with write-through cache Personal computer having memory system with write-through cache

1991-12-20

1994-08-23

Chan, Eddie P.

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395375, 364DIG1, 36424341, 3642716, 3642718, 364263, 3642384, 36494834, 36496434, G06F 1200, G06F 938

Patent

active

053414870

ABSTRACT:
A personal computer has a memory system including a write-through cache which is accessible by more than one device. A snoop mechanism includes logic that monitors bus master control signals to determine if a new memory write cycle has been started before a current snoop cycle has finished. If a new cycle has been started, then a corresponding snoop cycle occurs which overlaps the new memory cycle and is pipelined with the previous snoop cycle so that the snooping mechanism does not fall behind the memory write cycles.

REFERENCES:
patent: 4392200 (1983-07-01), Arulpragasam et al.
patent: 4638431 (1987-01-01), Nishimura
patent: 5025365 (1991-06-01), Mathur et al.
patent: 5091846 (1992-02-01), Sachs et al.
patent: 5119485 (1992-06-01), Ledbetter, Jr. et al.
patent: 5193170 (1993-03-01), Lam
IBM Technical Disclosure Bulletin, vol. 34, No. 1, Jun. 1991, New York US pp. 254-256 "Fixed-length pepelined-bus-protocol for snoop cache".

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