Personal computer apparatus and method for monitoring memory loc

Details Personal computer apparatus and method for monitoring memory loc Personal computer apparatus and method for monitoring memory loc

1994-06-27

1998-12-15

Pan, Daniel H.

Boots, shoes, and leggings

3642217, 364267, 3642674, 36426791, 3642978, 3642694, 364DIG1, 364DIG2, 395700, 39518316, 39518307, G06F 124, G06F 924, G06F 1128, G06F 1134

Patent

active

058505628

ABSTRACT:
A monitor and debugger routine operable on a personal computer for facilitating the design of power-on self-test (POST) and basic input and output system (BIOS) code. The monitor and debugger routine is invoked by POST code early in the system initialization process, before most of the system hardware devices have been initialized and before the operating system has been invoked. The monitor and debugger routine uses minimal system resources--lower memory and a serial communications controller--and is accessed via an external communications and display device connected via a serial communications link generated by the serial communications controller. As so invoked, the monitor and debugger routine can be used to facilitate the design and debugging of the remaining portions of the system initialization code, hardware interface code, suspend and resume code, video code, and other code that cannot be debugged using standard debuggers that require a functioning BIOS and an operating system to operate.

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patent: 5047926 (1991-09-01), Kuo et al.
patent: 5093914 (1992-03-01), Coplien et al.
Motorola Microcomputer Development Systems--Low Cost MPU/MCU Evaluation Modules, Motorola Microprocessors, Series C, Motorola Inc., 1983, pp. 8-10 .

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